Patents by Inventor Tom Kwan
Tom Kwan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9577662Abstract: A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide the digital output signal. The CT-SDADC achieves the analog-to-digital conversion and ELDC by switching between two phases in the SAR sub-ADC: a sampling phase and a conversion phase. During the sampling phase, the SAR sub-ADC captures the analog input signal across multiple arrays of switchable capacitors. The conversion phase comprises a number of steps, and one or more bits of the digital output signal are resolved at each step of the conversion phase. A portion of the SC-DAC is driven by the delayed CT-SDADC output during the conversion phase to effectively compensate for excess loop delay caused by the CT-SDADC feedback loop.Type: GrantFiled: November 30, 2015Date of Patent: February 21, 2017Assignee: Broadcom CorporationInventors: Guowen Wei, Xinyu Yu, Michael Inerfield, Tom Kwan
-
Publication number: 20160233872Abstract: A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide the digital output signal. The CT-SDADC achieves the analog-to-digital conversion and ELDC by switching between two phases in the SAR sub-ADC: a sampling phase and a conversion phase. During the sampling phase, the SAR sub-ADC captures the analog input signal across multiple arrays of switchable capacitors. The conversion phase comprises a number of steps, and one or more bits of the digital output signal are resolved at each step of the conversion phase. A portion of the SC-DAC is driven by the delayed CT-SDADC output during the conversion phase to effectively compensate for excess loop delay caused by the CT-SDADC feedback loop.Type: ApplicationFiled: November 30, 2015Publication date: August 11, 2016Applicant: BROADCOM CORPORATIONInventors: Guowen WEI, Xinyu Yu, Michael Inerfield, Tom Kwan
-
Patent number: 8208462Abstract: A second output transmission signal (“TX2”) added to a line driver is a scaled version of the main output transmission signal (“TX1”). TX2 is scaled from TX1 by a variable scale factor K. An adaptive hybrid circuit subtracts TX1 and TX2 from a line signal carrying both a line transmission signal and a line received signal (“RX”). A programmable impedance Ztune is coupled between the TX2 output of the line driver and the RX output of the adaptive hybrid circuit. A transmission echo in the output RX signal is measured. K and Ztune are then adaptively tuned to minimize the transmission echo. The hybrid in this case becomes a 4-port network, one port specifically added to adaptively cancel the transmission echo in the RX output of the adaptive hybrid circuit. Alternatively, the hybrid may be a 3-port hybrid including variable impedances to cancel the line transmission signal.Type: GrantFiled: July 2, 2009Date of Patent: June 26, 2012Assignee: Broadcom CorporationInventors: Tom Kwan, Sumant Ranganathan
-
Patent number: 8026769Abstract: A frequency-locked clock generator includes a voltage-controlled oscillator (VCO), a frequency-to-current converter, a reference current source and a gain stage. The VCO generates an output signal. The frequency-to-current converter generates a converter current proportional to a frequency of the output signal. The reference current source generates a reference current. The gain stage generates a control signal based on a difference between the converter current and the reference current. The control signal is applied to the VCO to adjust the frequency of the output signal. Feedback forces the VCO to generate an output clock signal such that the corresponding current it produces (i.e., the converter current) is equal to the reference current. When in lock, the frequency of the output signal is determined by a time constant (or equivalent time constant) of the frequency-locked clock generator.Type: GrantFiled: December 14, 2009Date of Patent: September 27, 2011Assignee: Broadcom CorporationInventors: Tom Kwan, Niug Li
-
Patent number: 8018361Abstract: The present invention relates generally to analog-to-digital converters (ADCs). Embodiments of the present invention provide novel ADC architectures directed at reducing the overall ADC area and power consumption. Embodiments of the present invention may be used in pipelined ADCs, cyclic ADCs, and successive approximation (SAR) ADCs, for example. Further, embodiments of the present invention may be implemented using both single-ended and differential configurations.Type: GrantFiled: November 10, 2009Date of Patent: September 13, 2011Assignee: Broadcom CorporationInventors: Sumant Ranganathan, Tom Kwan, Xinyu Yu
-
Patent number: 7852058Abstract: An integrated circuit and method in an integrated circuit for providing electrical power utilizing digital power regulation. Various aspects of the present invention provide an integrated circuit comprising a power supply module that outputs electrical power at an output voltage level. An error determination module may receive a power supply reference signal and a signal indicative of the output voltage level and output a power supply error signal. A digital controller module may receive the power supply error signal, digitally process the power supply error signal, and output a power supply control signal. A power output-monitoring module may monitor the electrical power output from the power supply module and output the signal indicative of the output voltage level. The power supply module may receive the power supply control signal and output the electrical power based, at least in part, on the power supply control signal.Type: GrantFiled: January 11, 2010Date of Patent: December 14, 2010Assignee: Broadcom CorporationInventor: Tom Kwan
-
Publication number: 20100176977Abstract: The present invention relates generally to analog-to-digital converters (ADCs). Embodiments of the present invention provide novel ADC architectures directed at reducing the overall ADC area and power consumption. Embodiments of the present invention may be used in pipelined ADCs, cyclic ADCs, and successive approximation (SAR) ADCs, for example. Further, embodiments of the present invention may be implemented using both single-ended and differential configurations.Type: ApplicationFiled: November 10, 2009Publication date: July 15, 2010Applicant: Broadcom CorporationInventors: Sumant Ranganathan, Tom Kwan, Xinyu Yu
-
Publication number: 20100134191Abstract: A frequency-locked clock generator includes a voltage-controlled oscillator (VCO), a frequency-to-current converter, a reference current source and a gain stage. The VCO generates an output signal. The frequency-to-current converter generates a converter current proportional to a frequency of the output signal. The reference current source generates a reference current. The gain stage generates a control signal based on a difference between the converter current and the reference current. The control signal is applied to the VCO to adjust the frequency of the output signal. Feedback forces the VCO to generate an output clock signal such that the corresponding current it produces (i.e., the converter current) is equal to the reference current. When in lock, the frequency of the output signal is determined by a time constant (or equivalent time constant) of the frequency-locked clock generator.Type: ApplicationFiled: December 14, 2009Publication date: June 3, 2010Applicant: Broadcom CorporationInventors: Tom KWAN, Niug Li
-
Publication number: 20100109632Abstract: An integrated circuit and method in an integrated circuit for providing electrical power utilizing digital power regulation. Various aspects of the present invention provide an integrated circuit comprising a power supply module that outputs electrical power at an output voltage level. An error determination module may receive a power supply reference signal and a signal indicative of the output voltage level and output a power supply error signal. A digital controller module may receive the power supply error signal, digitally process the power supply error signal, and output a power supply control signal. A power output-monitoring module may monitor the electrical power output from the power supply module and output the signal indicative of the output voltage level. The power supply module may receive the power supply control signal and output the electrical power based, at least in part, on the power supply control signal.Type: ApplicationFiled: January 11, 2010Publication date: May 6, 2010Applicant: Broadcom CorporationInventor: Tom Kwan
-
Patent number: 7649345Abstract: An integrated circuit and method in an integrated circuit for providing electrical power utilizing digital power regulation. Various aspects of the present invention provide an integrated circuit comprising a power supply module that outputs electrical power at an output voltage level. An error determination module may receive a power supply reference signal and a signal indicative of the output voltage level and output a power supply error signal. A digital controller module may receive the power supply error signal, digitally process the power supply error signal, and output a power supply control signal. A power output-monitoring module may monitor the electrical power output from the power supply module and output the signal indicative of the output voltage level. The power supply module may receive the power supply control signal and output the electrical power based, at least in part, on the power supply control signal.Type: GrantFiled: April 20, 2005Date of Patent: January 19, 2010Assignee: Broadcom CorporationInventor: Tom Kwan
-
Publication number: 20090268646Abstract: A second output transmission signal (“TX2”) added to a line driver is a scaled version of the main output transmission signal (“TX1”). TX2 is scaled from TX1 by a variable scale factor K. An adaptive hybrid circuit subtracts TX1 and TX2 from a line signal carrying both a line transmission signal and a line received signal (“RX”). A programmable impedance Ztune is coupled between the TX2 output of the line driver and the RX output of the adaptive hybrid circuit. A transmission echo in the output RX signal is measured. K and Ztune are then adaptively tuned to minimize the transmission echo. The hybrid in this case becomes a 4-port network, one port specifically added to adaptively cancel the transmission echo in the RX output of the adaptive hybrid circuit. Alternatively, the hybrid may be a 3-port hybrid including variable impedances to cancel the line transmission signal.Type: ApplicationFiled: July 2, 2009Publication date: October 29, 2009Applicant: Broadcom CorporationInventors: Tom Kwan, Sumant Ranganathan
-
Patent number: 7573839Abstract: A second output transmission signal (“TX2”) added to a line driver is a scaled version of the main output transmission signal (“TX1”). TX2 is scaled from TX1 by a variable scale factor K. An adaptive hybrid circuit subtracts TX1 and TX2 from a line signal carrying both a line transmission signal and a line received signal (“RX”). A programmable impedance Ztune is coupled between the TX2 output of the line driver and the RX output of the adaptive hybrid circuit. A transmission echo in the output RX signal is measured. K and Ztune are then adaptively tuned to minimize the transmission echo. The hybrid in this case becomes a 4-port network, one port specifically added to adaptively cancel the transmission echo in the RX output of the adaptive hybrid circuit. Alternatively, the hybrid may be a 3-port hybrid including variable impedances to cancel the line transmission signal.Type: GrantFiled: December 3, 2004Date of Patent: August 11, 2009Assignee: Broadcom CorporationInventors: Tom Kwan, Sumant Ranganathan
-
Patent number: 7453943Abstract: A hybrid circuit that decouples gains for a transmit signal and a receive signal of a broadband modem that is coupled to a telephone line is provided. The hybrid circuit includes a multi-port transformer, a pair of line matching resistors, and a bridge circuit. The multi-port transformer includes a line coil electrically coupled to a telephone line, a linedriver coil magnetically coupled to the line coil and a receive coil that is also magnetically coupled to the line coil. In an alternate embodiment, a hybrid circuit is provided that includes a multi-port transformer in which the line coil, linedriver coil and receive coil include two coil segments. A broadband modem incorporating a hybrid circuit of the present invention is also provided.Type: GrantFiled: October 27, 2003Date of Patent: November 18, 2008Assignee: Broadcom CorporationInventors: Augustine Kuo, Tom Kwan, Sumant Ranganathan
-
Publication number: 20080068091Abstract: A frequency-locked clock generator includes a voltage-controlled oscillator (VCO), a frequency-to-current converter, a reference current source and a gain stage. The VCO generates an output signal. The frequency-to-current converter generates a converter current proportional to a frequency of the output signal. The reference current source generates a reference current. The gain stage generates a control signal based on a difference between the converter current and the reference current. The control signal is applied to the VCO to adjust the frequency of the output signal. Feedback forces the VCO to generate an output clock signal such that the corresponding current it produces (i.e., the converter current) is equal to the reference current. When in lock, the frequency of the output signal is determined by a time constant (or equivalent time constant) of the frequency-locked clock generator.Type: ApplicationFiled: May 19, 2006Publication date: March 20, 2008Applicant: Broadcom CorporationInventors: Tom Kwan, Ning Li
-
Publication number: 20070252745Abstract: An analog-to-digital converter (ADC) disposed in a data reception path to convert data from an analog format to a digital format is switched between two or more power modes to conserve power when data is not being received. ADC stays in a lower power-lower precision mode until an inbound data is detected, at which time the ADC switches to a higher power-higher precision mode to convert the data. Once data conversion is completed, the ADC switches back to the lower power-lower precision mode to conserve power.Type: ApplicationFiled: June 29, 2007Publication date: November 1, 2007Applicant: Broadcom Corporation, a California CorporationInventors: Srinivasa Garlapati, Paul Lettieri, Jason Trachewsky, Gregory Efland, Tom Kwan
-
Publication number: 20070114984Abstract: Embodiment of the present invention may provide a switching regulator which may be located within an IC. The switching regulator couples to an external power supply, a plurality of configurable control registers, a plurality of default registers, and a multiplexer. The multiplexer is operable to select an input control signal from either the plurality of configurable control registers or the plurality of default control registers as the output control signal to the switching regulator. This default control signal, although not optimal, allows the switching regulator to be configured in a default condition during start up or power down operations and ensures that the switching regulator may provide a stable, although not necessarily optimal, power output to the various components within the IC.Type: ApplicationFiled: November 21, 2005Publication date: May 24, 2007Inventors: Ning Li, Tom Kwan
-
Publication number: 20070077908Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.Type: ApplicationFiled: March 31, 2006Publication date: April 5, 2007Applicant: Broadcom CorporationInventors: Pieter Vorenkamp, Klaas Bult, Frank Carr, Christopher Ward, Ralph Duncan, Tom Kwan, James Chang, Haideh Khorramabadi
-
Publication number: 20070001889Abstract: An analog-to-digital converter (ADC) disposed in a data reception path to convert data from an analog format to a digital format is switched between two or more power modes to conserve power when data is not being received. ADC stays in a lower power-lower precision mode until an inbound data is detected, at which time the ADC switches to a higher power-higher precision mode to convert the data. Once data conversion is completed, the ADC switches back to the lower power-lower precision mode to conserve power.Type: ApplicationFiled: September 5, 2006Publication date: January 4, 2007Applicant: Broadcom Corporation, a California CorporationInventors: Srinivasa Garlapati, Paul Lettieri, Jason Trachewsky, Gregory Efland, Tom Kwan
-
Publication number: 20060238256Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.Type: ApplicationFiled: May 2, 2006Publication date: October 26, 2006Inventors: Arya Behzad, Klaas Bult, Ramon Gomez, Chi-Hung Lin, Tom Kwan, Oscar Agazzi, John Creigh, Mehdi Hatamian, David Kruse, Arthur Abnous, Henry Samueli
-
Publication number: 20060202755Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal, By isolating the switches from the signal path linearity of the PGA can be improved.Type: ApplicationFiled: May 25, 2006Publication date: September 14, 2006Inventors: Arya Behzad, Klaas Bult, Ramon Gomez, Chi-Hung Lin, Tom Kwan, Oscar Agazzi, John Creigh, Mehdi Hatamian, David Kruse, Arthur Abnous, Henry Samueli