Patents by Inventor Tom L. Nguyen
Tom L. Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11113188Abstract: Combined operational steps and device characteristics help preserve data against integrity threats. Data is divided into critical data and non-critical data, based on criteria such as customer requirements, workload criticality, or virtual machine criticality. Data may be generated in a compute node for storage in a storage node, for example. Critical data is stored in a battery-backed memory aperture at physical addresses where it will be flushed ahead of the non-critical data due to a flush order imposed by or on the battery-backed memory, e.g., a bottom-up NVDIMM flush order. Redundant copies of the data (especially non-critical data) may also be kept in case it does not get flushed in time. Battery-backed memory apertures are sized and located according to their battery's characteristics, and may be relocated or resized as conditions change. Flush defragging is performed to optimize use of the aperture, especially within the portion that holds critical data.Type: GrantFiled: August 21, 2019Date of Patent: September 7, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Mallik Bulusu, Tom L. Nguyen, Neeraj Ladkani, Ravi Mysore Shantamurthy
-
Publication number: 20210056016Abstract: Combined operational steps and device characteristics help preserve data against integrity threats. Data is divided into critical data and non-critical data, based on criteria such as customer requirements, workload criticality, or virtual machine criticality. Data may be generated in a compute node for storage in a storage node, for example. Critical data is stored in a battery-backed memory aperture at physical addresses where it will be flushed ahead of the non-critical data due to a flush order imposed by or on the battery-backed memory, e.g., a bottom-up NVDIMM flush order. Redundant copies of the data (especially non-critical data) may also be kept in case it does not get flushed in time. Battery-backed memory apertures are sized and located according to their battery's characteristics, and may be relocated or resized as conditions change. Flush defragging is performed to optimize use of the aperture, especially within the portion that holds critical data.Type: ApplicationFiled: August 21, 2019Publication date: February 25, 2021Inventors: Mallik BULUSU, Tom L. NGUYEN, Neeraj LADKANI, Ravi MYSORE SHANTAMURTHY
-
Patent number: 10713128Abstract: In some examples, error recovery in volatile memory regions may include determining, during a save operation that includes saving of data to a primary location, that an error occurred with respect to the save operation. Based on a determination that the error occurred with respect to the save operation, an error location may be determined, and a determination may be made as to whether the error location maps to a volatile memory region. Based on a determination that the error location maps to the volatile memory region, a reserved location may be identified for saving the data. The data may be saved from the primary location to the reserved location. Further, metadata may be updated to indicate usage of the reserved location as the primary location for the saved data.Type: GrantFiled: November 30, 2017Date of Patent: July 14, 2020Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tom L. Nguyen, Mallik Bulusu
-
Patent number: 10635553Abstract: In some examples, error recovery in non-volatile storage partitions may include determining, upon completion of a save operation that includes saving of data to a primary location, that an error occurred with respect to the save operation. Based on a determination that the error occurred with respect to the save operation, a reserved location for saving the data may be identified. The data may be saved to the reserved location. Metadata to indicate usage of the reserved location as the primary location for the saved data may be updated.Type: GrantFiled: October 20, 2017Date of Patent: April 28, 2020Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Mallik Bulusu, Tom L. Nguyen
-
Publication number: 20190163557Abstract: In some examples, error recovery in volatile memory regions may include determining, during a save operation that includes saving of data to a primary location, that an error occurred with respect to the save operation. Based on a determination that the error occurred with respect to the save operation, an error location may be determined, and a determination may be made as to whether the error location maps to a volatile memory region. Based on a determination that the error location maps to the volatile memory region, a reserved location may be identified for saving the data. The data may be saved from the primary location to the reserved location. Further, metadata may be updated to indicate usage of the reserved location as the primary location for the saved data.Type: ApplicationFiled: November 30, 2017Publication date: May 30, 2019Applicant: Microsoft Technology Licensing, LLCInventors: Tom L. NGUYEN, Mallik BULUSU
-
Publication number: 20190121710Abstract: In some examples, error recovery in non-volatile storage partitions may include determining, upon completion of a save operation that includes saving of data to a primary location, that an error occurred with respect to the save operation. Based on a determination that the error occurred with respect to the save operation, a reserved location for saving the data may be identified. The data may be saved to the reserved location. Metadata to indicate usage of the reserved location as the primary location for the saved data may be updated.Type: ApplicationFiled: October 20, 2017Publication date: April 25, 2019Applicant: Microsoft Technology Licensing, LLCInventors: Mallik BULUSU, Tom L. NGUYEN
-
Patent number: 10115442Abstract: A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A number of pages that may be treated as non-volatile may be determined based on demand for non-volatile storage by at least one application executing on the computing device.Type: GrantFiled: August 30, 2016Date of Patent: October 30, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Bryan D. Kelly, Mallik Bulusu, Ravi Mysore Shantamurthy, Tom L. Nguyen
-
Publication number: 20170212687Abstract: A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A number of pages that may be treated as non-volatile may be determined based on demand for non-volatile storage by at least one application executing on the computing device.Type: ApplicationFiled: August 30, 2016Publication date: July 27, 2017Inventors: Bryan D. Kelly, Mallik Bulusu, Ravi Mysore Shantamurthy, Tom L. Nguyen
-
Patent number: 7496706Abstract: In some embodiments, the inventions include a chip having a message signaled interrupt redirection table (MRT) that contains entries including an address field and a data field. The chip also includes translation circuitry to translate an address field and a data field of a message signaled interrupt (MSI) signal by copying contents of the address field and data field of an entry in the MRT into the address field and data field of the MSI. Other embodiments are described and claimed.Type: GrantFiled: June 30, 2004Date of Patent: February 24, 2009Assignee: Intel CorporationInventors: Tom L. Nguyen, Steven R. Carbonari
-
Patent number: 7434068Abstract: Content stored in a non-volatile storage device is protected from unauthorized modification and/or access. The device is configured as one or more regions, where one or more of the regions implements one or more content protection schemes. The current version of the contents stored in a region is compared to a previously stored valid version to determine if the current version has been modified without authorization. A region may be protected by use of an integrity metric (e.g., checksum, bit mask, and/or cyclic redundancy check value). The methodology may be implemented during the start up sequence of a computer system to protect the basic I/O system (BIOS) from unauthorized modification.Type: GrantFiled: October 19, 2001Date of Patent: October 7, 2008Assignee: Intel CorporationInventors: Tom L. Nguyen, Mallik Bulusu
-
Patent number: 7073006Abstract: A system and method for implementing hardware event driven soft real-time interrupts on a serial bus. In one embodiment, the serial bus comprises a universal serial bus. One embodiment of the presently described system includes a client device coupled to a host device. In one embodiment, the host places the client device in an interrupt mode by causing the client device to enter a suspend state. While in the interrupt mode, the client device sends an interrupt request signal to indicate it has interrupt data. In one embodiment, the host device indicates to the client device to enter the interrupt mode by sending a set interrupt mode signal. In response, the client device enters the interrupt mode and sends an interrupt request signal to the host to indicate it has interrupt data.Type: GrantFiled: August 2, 2001Date of Patent: July 4, 2006Assignee: Intel CorporationInventor: Tom L. Nguyen
-
Patent number: 6990542Abstract: A system and method for implementing hardware event driven soft real-time interrupts on a serial bus. In one embodiment, the serial bus comprises a universal serial bus. One embodiment of the presently described system includes a client device coupled to a host device. In one embodiment, the host places the client device in an interrupt mode by causing the client device to enter a suspend state. While in the interrupt mode, the client device sends an interrupt request signal to indicate it has interrupt data. In one embodiment, the host device indicates to the client device to enter the interrupt mode by sending a set interrupt mode signal. In response, the client device enters the interrupt mode and sends an interrupt request signal to the host to indicate it has interrupt data.Type: GrantFiled: May 7, 2004Date of Patent: January 24, 2006Assignee: Intel CorporationInventor: Tom L. Nguyen
-
Publication number: 20040210698Abstract: A system and method for implementing hardware event driven soft real-time interrupts on a serial bus. In one embodiment, the serial bus comprises a universal serial bus. One embodiment of the presently described system includes a client device coupled to a host device. In one embodiment, the host places the client device in an interrupt mode by causing the client device to enter a suspend state. While in the interrupt mode, the client device sends an interrupt request signal to indicate it has interrupt data. In one embodiment, the host device indicates to the client device to enter the interrupt mode by sending a set interrupt mode signal. In response, the client device enters the interrupt mode and sends an interrupt request signal to the host to indicate it has interrupt data.Type: ApplicationFiled: May 7, 2004Publication date: October 21, 2004Inventor: Tom L. Nguyen
-
Publication number: 20030079138Abstract: One aspect of the invention provides a novel scheme to protect content stored in a non-volatile storage device from unauthorized modifications and/or access. The non-volatile storage device is configured as one or more regions, one or more of the regions implementing one or more content protection schemes. The current version of content stored in a region is compared to a previously stored valid version of the content to determine if the current version has been modified without authorization. A region may be protected by use of an integrity metric (e.g. checksum, bit mask, and/or cyclic redundancy check value).Type: ApplicationFiled: October 19, 2001Publication date: April 24, 2003Inventors: Tom L. Nguyen, Mallik Bulusu
-
Publication number: 20030070115Abstract: A number of correctable and uncorrectable errors, including machine check aborts and system-hang events, may occur during the pre-boot stage prior to operation of an operating system. Outside of a laboratory environment, for example, in the field, it is very difficult to obtain this error information. By logging the error information during the pre-boot stage, the logged error information may thereafter be transferred to an appropriate media or over a ii network for subsequent analysis. This pre-boot logging and subsequent retrieval may enable correction of pre-boot errors that otherwise may go unanalyzed and repeatedly reoccur.Type: ApplicationFiled: October 5, 2001Publication date: April 10, 2003Inventors: Tom L. Nguyen, Mallik Bulusu
-
Publication number: 20030028697Abstract: A system and method for implementing hardware event driven soft real-time interrupts on a serial bus. In one embodiment, the serial bus comprises a universal serial bus. One embodiment of the presently described system includes a client device coupled to a host device. In one embodiment, the host places the client device in an interrupt mode by causing the client device to enter a suspend state. While in the interrupt mode, the client device sends an interrupt request signal to indicate it has interrupt data. In one embodiment, the host device indicates to the client device to enter the interrupt mode by sending a set interrupt mode signal. In response, the client device enters the interrupt mode and sends an interrupt request signal to the host to indicate it has interrupt data.Type: ApplicationFiled: August 2, 2001Publication date: February 6, 2003Inventor: Tom L. Nguyen