Abstract: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.

Abstract: A signal buffer amplifier with high linearity is provided. A circuit includes a first transistor having a first gate terminal, a first source terminal, and a first drain terminal. The circuit also includes a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, the second drain terminal coupled to the first source terminal. The circuit further includes a first signal path coupled in between a signal input and the first gate terminal, a second signal path coupled in between the signal input and the second gate terminal, and a signal output coupled to the second source terminal. The first signal path includes a filter.

Abstract: In one embodiment, a circuit for generating a reference voltage between a first output and a second output, has a first follower transistor that includes a first control node, a first follower node coupled to a first output, and a first supply node, and a second follower transistor that includes a second control node, a second follower node coupled to a second output and a second supply node. A first voltage drop circuit is coupled between a circuit supply node and the second supply node. The circuit is biased such that the voltage between the circuit supply node and the second supply node is greater than the voltage between the circuit supply node and the first supply node, and such that the voltage between the circuit supply node and the second control node is greater than the voltage between the circuit supply node and the first control node.

Abstract: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.

Abstract: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.

Abstract: A signal buffer amplifier with high linearity is provided. A circuit includes a first transistor having a first gate terminal, a first source terminal, and a first drain terminal. The circuit also includes a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, the second drain terminal coupled to the first source terminal. The circuit further includes a first signal path coupled in between a signal input and the first gate terminal, a second signal path coupled in between the signal input and the second gate terminal, and a signal output coupled to the second source terminal. The first signal path includes a filter.

Abstract: In one embodiment, a circuit for generating a reference voltage between a first output and a second output, has a first follower transistor that includes a first control node, a first follower node coupled to a first output, and a first supply node, and a second follower transistor that includes a second control node, a second follower node coupled to a second output and a second supply node. A first voltage drop circuit is coupled between a circuit supply node and the second supply node. The circuit is biased such that the voltage between the circuit supply node and the second supply node is greater than the voltage between the circuit supply node and the first supply node, and such that the voltage between the circuit supply node and the second control node is greater than the voltage between the circuit supply node and the first control node.

Abstract: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.

Abstract: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices in the first side. A polymeric stiffener ring is formed on the first side. The stiffener ring embeds the first plurality of passive devices without covering a central portion of the first surface of the substrate. A semiconductor chip is mounted on the central portion of the first surface of the substrate.

Abstract: A method of sampling an input signal in a delta-sigma modulator having at least an integrator stage and a feedback digital-to-analog converter (DAC) stage includes sampling an input signal at a sampling rate by alternately utilizing the two sampling capacitors during two sampling cycles such that the two sampling capacitors are each being utilized at half the rate of the sampling rate. Samples from the two sampling capacitors are summed at the sampling rate at an intermediate node with a feedback samples provided by the feedback DAC stage at the sampling rate to generate output samples which are output from integrator stage at the sampling rate.

Abstract: An integrated circuit arrangement comprising an integrated circuit package having a package board. An integrated circuit die is mounted to a surface of the package board. A spring frame is mounted to the package board surface at a pair of opposite frame bends. The spring frame has a central opening that receives the integrated circuit die. Sides of the spring frame away from the bends are raised from the package surface. A heat sink is mounted to the spring frame such that a bottom of the heat sink contacts an upper surface of the integrated circuit die as the heat sink pushes the sides of the spring frame toward the package surface.

Abstract: An integrated circuit arrangement having an integrated circuit package contains an integrated circuit device mounted to a surface of the package. A flat frame is placed on the package surface and substantially surrounds the device. The flat frame has a central opening that receives the integrated circuit device. The height of the flat frame is relative to the height of the circuit device. A heat sink is mounted to the circuit device such that the bottom of the heat sink contacts the upper surface of the integrated circuit device but, does not contact the flat frame.

Abstract: Improved thermal characteristics are obtained in a multi-layer substrate for mounting a semiconductor device. A prepeg layer disposed in close proximity to or immediately adjacent to a semiconductor device is formed incorporating an integral, thermally-conductive mesh or screen. The prepeg layer is preferably a sandwich structure of two BT-resin layers (films), between which is disposed a copper screen. In this manner, heat is conducted away from an operating device by an integral part of the substrate, without the need for additional slugs or heat sink structures. Utility for multichip modules is also disclosed.

Abstract: Wells are formed in an external surface of a semiconductor device package body. Capacitors are disposed within the wells at least partially, and preferably fully within the body. Cleaning channels are formed underneath the capacitors, for removing residual flux and/or solder.

Abstract: Wells are formed in an external surface of a semiconductor device package body. Capacitors are disposed within the wells at least partially, and preferably fully within the body. Cleaning channels are formed underneath the capacitors, for removing residual flux and/or solder.