Patents by Inventor Tom M. Skoric

Tom M. Skoric has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6092134
    Abstract: A computer system includes a bus. A first connector is coupled to the bus. A first processor is coupled to the first connector. A second connector is coupled to the bus. A lock-out unit is coupled to the first and second connectors. The lock-out unit disables the first processor in response to a slot occupation signal that indicates when one of a second processor and a termination card is not coupled to the second connector. By disabling the first processor when a termination card or processor does not occupy one of the slots, data corruption due to improper bus termination is prevented.
    Type: Grant
    Filed: May 21, 1998
    Date of Patent: July 18, 2000
    Assignee: Intel Corporation
    Inventors: Collier S. Chun, Tom M. Skoric
  • Patent number: 5870290
    Abstract: An interface adapter board according to the present invention can be inserted directly between two electronic parts without substantially displacing the electronic parts laterally. An electronic circuit board may include: (a) a first electronic part having a first array of conductors; (b) a second electronic part having a second array of conductors; and (c) an interface adapter board placed between the first and second electronic parts in such a way to minimize the lateral distance between each conductor of the first array and its respective conductor of the second array. The interface adapter board has a third array of conductors and a fourth array of conductors formed through the interface adapter board and positioned in an interstitial relationship with the third array of conductors. Each conductor of the first array is coupled to its respective conductor of the third array. A first set of conductors of the third array is directly coupled to its respective set of conductors of the fourth array.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: February 9, 1999
    Assignee: Intel Corporation
    Inventors: Collier S.C. Chun, Tom M. Skoric