Abstract: Described herein is a battery system that allows a battery pack to operate in different modes at different times. Each of the different modes may provide its own set of functionality that affects how the battery pack operates and/or reacts to external input signals. A mode may change how the battery pack discharges power by, for example, altering whether terminals are enabled or disabled. A mode may change how the battery pack's hardware operates by, for example, disabling or enabling portions of the battery pack's hardware. A mode may change what battery-related services are provided by the battery pack and available to an end user by, for example, enabling or disabling the sending of battery status information from the battery pack.

Abstract: Filling out the space of Redundant Array of Disks (RAID) format changes during drive capacity and count changes, including: detecting, in a storage system having a first Redundant Array of Independent Disks (RAID) format, a change to an operational characteristic of the storage system; and reconfiguring the storage system to have a second RAID format in response to the detected change.

Abstract: Described herein is a battery system that allows a battery pack to operate in different modes at different times. Each of the different modes may provide its own set of functionality that affects how the battery pack operates and/or reacts to external input signals. A mode may change how the battery pack discharges power by, for example, altering whether terminals are enabled or disabled. A mode may change how the battery pack's hardware operates by, for example, disabling or enabling portions of the battery pack's hardware. A mode may change what battery-related services are provided by the battery pack and available to an end user by, for example, enabling or disabling the sending of battery status information from the battery pack.

Abstract: Described herein is a battery system that allows a battery pack to operate in different modes at different times. Each of the different modes may provide its own set of functionality that affects how the battery pack operates and/or reacts to external input signals. A mode may change how the battery pack discharges power by, for example, altering whether terminals are enabled or disabled. A mode may change how the battery pack's hardware operates by, for example, disabling or enabling portions of the battery pack's hardware. A mode may change what battery-related services are provided by the battery pack and available to an end user by, for example, enabling or disabling the sending of battery status information from the battery pack.

Abstract: Described herein is a battery system that allows a battery pack to operate in different modes at different times. Each of the different modes may provide its own set of functionality that affects how the battery pack operates and/or reacts to external input signals. A mode may change how the battery pack discharges power by, for example, altering whether terminals are enabled or disabled. A mode may change how the battery pack's hardware operates by, for example, disabling or enabling portions of the battery pack's hardware. A mode may change what battery-related services are provided by the battery pack and available to an end user by, for example, enabling or disabling the sending of battery status information from the battery pack.

Abstract: Described herein is a battery system that allows a battery pack to operate in different modes at different times. Each of the different modes may provide its own set of functionality that affects how the battery pack operates and/or reacts to external input signals. A mode may change how the battery pack discharges power by, for example, altering whether terminals are enabled or disabled. A mode may change how the battery pack's hardware operates by, for example, disabling or enabling portions of the battery pack's hardware. A mode may change what battery-related services are provided by the battery pack and available to an end user by, for example, enabling or disabling the sending of battery status information from the battery pack.

Abstract: Described herein is a battery system that allows a battery pack to operate in different modes at different times. Each of the different modes may provide its own set of functionality that affects how the battery pack operates and/or reacts to external input signals. A mode may change how the battery pack discharges power by, for example, altering whether terminals are enabled or disabled. A mode may change how the battery pack's hardware operates by, for example, disabling or enabling portions of the battery pack's hardware. A mode may change what battery-related services are provided by the battery pack and available to an end user by, for example, enabling or disabling the sending of battery status information from the battery pack.

Abstract: Embodiments of ensuring data integrity in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving, at a memory controller, a data request from the persistent storage to copy data from the memory. In response to the received data request, the requested data is retrieved from the memory. The retrieved data contains data bits and corresponding error correcting bits. The method can also include determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits. In response to determining that the retrieved data bits contain one or more data integrity errors, the memory controller can write data representing existence of the one or more data integrity errors into a memory location accessible by the processor for ensuring data integrity.

Abstract: Embodiments of ensuring data integrity in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving, at a memory controller, a data request from the persistent storage to copy data from the memory. In response to the received data request, the requested data is retrieved from the memory. The retrieved data contains data bits and corresponding error correcting bits. The method can also include determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits. In response to determining that the retrieved data bits contain one or more data integrity errors, the memory controller can write data representing existence of the one or more data integrity errors into a memory location accessible by the processor for ensuring data integrity.

Abstract: Embodiments of ensuring data integrity in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving, at a memory controller, a data request from the persistent storage to copy data from the memory. In response to the received data request, the requested data is retrieved from the memory. The retrieved data contains data bits and corresponding error correcting bits. The method can also include determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits. In response to determining that the retrieved data bits contain one or more data integrity errors, the memory controller can write data representing existence of the one or more data integrity errors into a memory location accessible by the processor for ensuring data integrity.

Abstract: Sensor packages and methods of assembling a sensor in a sensor package are provided. A preferred embodiment comprises: a base including a sensor coupled to the base wherein the base has at least one electrical connection location and a first mechanical mating interface in the shape of an arc; an electronics package with at least one electrical connection location; and a ring coupled between the base and the electronics package wherein the ring electrically connects the at least one electrical connection location on the base and the at least one electrical connection location on the electronics package and wherein the base has a second mechanical mating interface in the shape of an arc that is reciprocal to the first mating interface.

Abstract: Embodiments of ensuring data integrity in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving, at a memory controller, a data request from the persistent storage to copy data from the memory. In response to the received data request, the requested data is retrieved from the memory. The retrieved data contains data bits and corresponding error correcting bits. The method can also include determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits. In response to determining that the retrieved data bits contain one or more data integrity errors, the memory controller can write data representing existence of the one or more data integrity errors into a memory location accessible by the processor for ensuring data integrity.

Abstract: Embodiments of ensuring data integrity in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving, at a memory controller, a data request from the persistent storage to copy data from the memory. In response to the received data request, the requested data is retrieved from the memory. The retrieved data contains data bits and corresponding error correcting bits. The method can also include determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits. In response to determining that the retrieved data bits contain one or more data integrity errors, the memory controller can write data representing existence of the one or more data integrity errors into a memory location accessible by the processor for ensuring data integrity.

Abstract: A centrifuge device displays a workflow diagram during operation. The workflow diagram includes a loading step-indicator, a running step-indicator, and an unloading step-indicator. The loading step-indicator is displayed when the centrifuge device is operating in a loading mode. The running step-indicator is displayed when the centrifuge device is operating in a running mode. The unloading step-indicator is displayed when the centrifuge device is operating in the unloading mode. A centrifuge system includes the centrifuge device and a handheld device operable remote from the centrifuge device, which displays a status of the centrifuge device. Methods of operating a centrifuge device and a centrifuge system are also disclosed.

Abstract: Embodiments of ensuring data integrity in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving, at a memory controller, a data request from the persistent storage to copy data from the memory. In response to the received data request, the requested data is retrieved from the memory. The retrieved data contains data bits and corresponding error correcting bits. The method can also include determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits. In response to determining that the retrieved data bits contain one or more data integrity errors, the memory controller can write data representing existence of the one or more data integrity errors into a memory location accessible by the processor for ensuring data integrity.

Abstract: Sensor packages and methods of assembling a sensor in a sensor package are provided. A preferred embodiment comprises: a base including a sensor coupled to the base wherein the base has at least one electrical connection location and a first mechanical mating interface in the shape of an arc; an electronics package with at least one electrical connection location; and a ring coupled between the base and the electronics package wherein the ring electrically connects the at least one electrical connection location on the base and the at least one electrical connection location on the electronics package and wherein the base has a second mechanical mating interface in the shape of an arc that is reciprocal to the first mating interface.