Abstract: A continuous-time modulator comprises a modulator bridge having a bridge input terminal, an inverted bridge input terminal, a clock terminal and an inverted clock terminal. The modulator further comprises an input amplifier for amplifying an input signal and the input signal inverted and a bridge amplifier coupled to the input amplifier. The bridge is coupled to the bridge amplifier. The modulator further comprises a feedback amplifier coupled to the bridge, with the bridge amplifier coupled to the feedback amplifier. A clock amplifier for amplifying a clock signal and the clock signal inverted is also coupled to the bridge. An output signal is provided at an output terminal coupled to the bridge input terminal. An inverted output signal is provided at an output terminal coupled to the inverted bridge input terminal.

Abstract: A system for quantizing an analog signal comprises an input terminal for receiving an analog input signal, an inverted input terminal for receiving an inverted input signal, a clock terminal for receiving a clock signal, and an inverted clock terminal for receiving an inverted clock signal. A sample-and-hold circuit is coupled to the input terminal, the inverted input terminal, the clock terminal, and the inverted clock terminal. A comparator circuit is coupled to the sample-and-hold circuit, the clock terminal, and the inverted clock terminal. A latch circuit is coupled to the comparator circuit, the clock terminal, and the inverted clock terminal. An output terminal having a quantized output signal is coupled to the latch circuit. An inverted output terminal having an inverted output signal is coupled to the latch circuit.

Abstract: A system for quantizing an analog signal comprises an input terminal for receiving an analog input signal, a clock terminal for receiving a clock signal, and an inverted clock terminal for receiving an inverted clock signal. A first negative-resistance device has a first terminal coupled to the clock terminal and a second terminal coupled to the input terminal. A second negative-resistance device has a first terminal coupled to the input terminal and a second terminal coupled to the inverted clock terminal. An output terminal coupled to the first negative-resistance device and the second negative-resistance device to provide a quantized output signal.

Abstract: A continuous-time modulator comprises a modulator bridge having a bridge input terminal, an inverted bridge input terminal, a clock terminal and an inverted clock terminal. The modulator further comprises an input amplifier for amplifying an input signal and the input signal inverted and a bridge amplifier coupled to the input amplifier. The bridge is coupled to the bridge amplifier. The modulator further comprises a feedback amplifier coupled to the bridge, with the bridge amplifier coupled to the feedback amplifier. A clock amplifier for amplifying a clock signal and the clock signal inverted is also coupled to the bridge. An output signal is provided at an output terminal coupled to the bridge input terminal. An inverted output signal is provided at an output terminal coupled to the inverted bridge input terminal.

Abstract: An oscillator is provided that includes a plurality of bridges and a plurality of transmission lines. Each bridge includes a plurality of negative differential resistance devices. Each transmission line interconnects two adjacent bridges. A clock circuit is coupled to at least one of the bridges.

Abstract: A system for quantizing an analog signal comprises an input terminal for receiving an input signal, an inverted input terminal for receiving an inverted input signal, a clock terminal for receiving a clock signal, and an inverted clock terminal for receiving an inverted clock signal. A first negative-resistance device has a first terminal coupled to the clock terminal and a second terminal coupled to the clock terminal coupled to the input terminal. A second negative-resistance device has a third terminal coupled to the clock terminal and a fourth terminal coupled to the inverted input terminal. A third negative-resistance device has a fifth terminal coupled to the input terminal and a sixth terminal coupled to the inverted clock terminal. A fourth negative-resistance device has a seventh terminal coupled to the inverted input terminal and an eighth terminal coupled to the inverted clock terminal. An output terminal for producing an output signal is connected to the input terminal.

Abstract: A phase-locking system is provided that includes a bridge, a light source and an optical pulse injector. The bridge includes a plurality of negative differential resistance devices for storing an input signal. The light source is capable of producing an optical pulse. The optical pulse injector receives the optical pulse and transmits an optical signal to trigger the bridge in response to receiving the optical pulse.

Abstract: A system for storing digital data includes an input circuit, a clock circuit, and a bridge. The input circuit is coupled to receive an input signal. The clock circuit receives and transmits a clock signal. The bridge stores the digital data and includes a plurality of negative differential resistance devices. The bridge connects to the input circuit and the clock circuit.

Abstract: A system for quantizing an analog signal comprises an input terminal for receiving an analog input signal, an inverted input terminal for receiving an inverted input signal, a clock terminal for receiving a clock signal, and an inverted clock terminal for receiving an inverted clock signal. A sample-and-hold circuit is coupled to the input terminal, the inverted input terminal, the clock terminal, and the inverted clock terminal. A comparator circuit is coupled to the sample-and-hold circuit, the clock terminal, and the inverted clock terminal. A latch circuit is coupled to the comparator circuit, the clock terminal, and the inverted clock terminal. An output terminal having a quantized output signal is coupled to the latch circuit. An inverted output terminal having an inverted output signal is coupled to the latch circuit.

Abstract: A resonant tunneling diode (400) made of a quantum well (406) with tunneling barriers (404, 408) made of two different materials such as calcium fluoride (408) and silicon dioxide (404). The calcium fluoride provides lattice match between the emitter (410) and the quantum well (406). Further resonant tunneling diodes with silicon lattice match barriers may be made of III-V compounds containing nitrogen.

Abstract: A high-speed differential comparator is disclosed. The comparator (100) includes a transconductance device (102 through 112) that receives first and second input voltages (V.sub.IN and -V.sub.IN) and generates first and second currents in response to the first and second input voltages. A first resonant tunneling diode (118) conducts the first current and generates a first output voltage (V.sub.OUT1) at a first output terminal (105) in response to the first current. A second resonant tunneling diode (126) conducts the second current and generates a second output voltage (V.sub.OUT2) at a second output terminal (109) in response to the second current. The comparator responds to input voltages at high speed and may be used for high frequency signal sampling and level determination.

Abstract: A high-speed differential comparator (300) is disclosed. A transconductance device is connected to the input terminal and the first and second output terminals (305 and 309, respectively) of the comparator. The transconductance device receives an input voltage (V.sub.IN) from the input terminal and generates a current between the first and second output terminals (305 and 309) in response to the input voltage. A load is connected between the first and second output terminals. The load, which includes a resonant tunneling diode (313), conducts the current and generates a voltage difference between the first and second output terminals (305 and 309) in response to the current. The comparator responds to input voltages at high speed and may be used for high frequency signal sampling and level determination.

Abstract: A high frequency clock signal generator (10) is disclosed. The clock signal generator includes a power supply (12, 14), a first resonant tunneling diode (18) coupled to a first terminal of the power supply and an output node (22), and a second resonant tunneling diode (20) coupled to the output node (22) and a second terminal of the power supply. A signal source is coupled to the output node (22) and periodically switches the first and second resonant tunneling diodes (18, 20) between a first state and a second state. The signal source comprises an oscillating signal generator (26) and a transmission line (28) coupled to the output node (22) of the clock signal generator. The oscillating signal generator (26) produces an oscillating input signal, which is reflected by the transmission line (28). The resonant tunneling diode configuration provides rapid voltage swings at the output, thus allowing the generation of a high frequency clock signal of 25 GHz or more.

Abstract: A high speed digital static shift register includes a series-connected pair of resonant tunneling diodes (RTDs) 22, 24 to achieve a bistable operating state. A clocked switch 20 provides the means of setting the binary state of this bistable pair. In order for one bistable pair to drive a following pair, a method of providing isolation and gain using a buffer amplifier 26 between the two pairs of RTDs is also provided. In one embodiment, the buffer amplifier comprises enhancement FET 30 and depletion load FET 28.