Patents by Inventor Tom R. O'Connor

Tom R. O'Connor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip design method for designing integrated circuit chips with embedded memories
    Patent number: 6775811
    Abstract: A method of circuit design for designing integrated circuits with one or more embedded memories. A placement is generated for timing critical logic associated with each included embedded memory in a logic design. An augmented memory boundary is generated for said each included memory. Each augmented memory boundary encompasses one embedded memory and associated said timing critical logic.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: August 10, 2004
    Assignee: LSI Logic Corporation
    Inventors: Viswanathan Lakshmanan, Michael Josephides, Tom R. O'Brien, David A. Morgan
  • Chip design method for designing integrated circuit chips with embedded memories
    Publication number: 20030221177
    Abstract: A method of circuit design for designing integrated circuits with one or more embedded memories. A placement is generated for timing critical logic associated with each included embedded memory in a logic design. An augmented memory boundary is generated for said each included memory. Each augmented memory boundary encompasses one embedded memory and associated said timing critical logic.
    Type: Application
    Filed: May 22, 2002
    Publication date: November 27, 2003
    Applicant: LSI LOGIC CORPORATION
    Inventors: Viswanathan Lakshmanan, Michael Josephides, Tom R. O'Brien, David A. Morgan
  • Low cost, hermetic pin grid array package
    Patent number: 4861944
    Abstract: A pin grid array package includes an electrically insulating, moisture impervious base having a plurality of bores therethrough, electrically conducting pins extending through the bores, metallic collars wedged between the pins and the bores adjacent the bottom side of the base, an electrically conducting trace formed of a silver-2 percent platinum alloy extending from each pin to the location for attachment of an electrical device, and a melted eutectic bond between the metal of the conducting path and the head of the pin at the top side of the base.
    Type: Grant
    Filed: December 9, 1987
    Date of Patent: August 29, 1989
    Assignee: Cabot Electronics Ceramics, Inc.
    Inventors: Kenneth L. Jones, II, Tom R. O'Connor, Kenneth A. Trevellyan