Abstract: Determining the yaw angle of a trailer with respect to the longitudinal axis of a towing vehicle is disclosed. This includes capturing first and second images of the trailer using a camera. Trailer orientation with respect to the vehicle is different on the two images. First and second trailer features are determined which are visible on the two images. The first and second features are at different positions of the trailer. A first angle estimation is calculated characterizing the pivot angle in a horizontal plane between the first feature on the first image and the first feature on the second image relative to a towing vehicle fix point. A second angle estimation is calculated characterizing the pivot angle in a horizontal plane between the second feature on the first image and the second feature on the second image relative to the fix point. The yaw angle is calculated based on the first and second angle estimations.

Abstract: A method for harmonizing a combined image involves receiving a respective image or image frame from each of two or more cameras, the images from two of the cameras representing the same region in an overlap region, measuring pixel statistics of at least some of the pixels in the overlap region for the image of each of the two cameras, determining a difference in the pixel statistics ?pixel of the image from each of the two cameras in the overlap region, calculating a correction factor Kpixel, wherein the correction factor Kpixel may be predicted to produce a reduction in ?pixel of less than ?pixel/2 when applied to the image of one of the two cameras, applying the correction factor Kpixel in a hardware device acquiring the image, and receiving a further image or image frame from each of the two cameras.

Abstract: A method for harmonizing a combined image involves receiving a respective image or image frame from each of two or more cameras, the images from two of the cameras representing the same region in an overlap region, measuring pixel statistics of at least some of the pixels in the overlap region for the image of each of the two cameras, determining a difference in the pixel statistics ?pixel of the image from each of the two cameras in the overlap region, calculating a correction factor Kpixel, wherein the correction factor Kpixel may be predicted to produce a reduction in ?pixel of less than ?pixel/2 when applied to the image of one of the two cameras, applying the correction factor Kpixel in a hardware device acquiring the image, and receiving a further image or image frame from each of the two cameras.

Abstract: Methods and devices for forming a series of samples of a filtered version of an input signal. Multiple tap current cells each generate a tap current from the signal. Multiple distribution means couple the tap current cells with multiple integrating means. The distribution means is controlled by a first clock signal. The multiple integrating means integrate tap currents that they receive and these integrating means form the samples. The tap currents generated are each sent to each integrating means in a predetermined sequence according to the first clock signal. The integrating means each use integrating and sampling phases controlled by a second clock signal. During the integrating phase an integrating means receives tap currents in sequence, while during the rest phase, no tap currents are received and the contents of the circuit are sampled and the integrator means is reset.

Abstract: Methods and devices for forming a series of samples of a filtered version of an input signal. Multiple tap current cells each generate a tap current from the signal. Multiple distribution means couple the tap current cells with multiple integrating means. The distribution means is controlled by a first clock signal. The multiple integrating means integrate tap currents that they receive and these integrating means form the samples. The tap currents generated are each sent to each integrating means in a predetermined sequence according to the first clock signal. The integrating means each use integrating and sampling phases controlled by a second clock signal. During the integrating phase an integrating means receives tap currents in sequence, while during the rest phase, no tap currents are received and the contents of the circuit are sampled and the integrator means is reset.

Abstract: Methods, systems and components for use with or as a phase frequency detector. The phase frequency detector stretches its output pulse, allowing the detector to operate in a more linear region. As part of the invention, a new configuration for a D type flip flop is also disclosed. In one embodiment, the D type flip flop triggers at both the rising and the falling edges of the reference input, allowing a lower frequency input to be used while having the advantages of a higher frequency.

Abstract: Methods and devices for an improved delta sigma modulator. The delta sigma modulator has multiple filters with at least one high order filter processing the MSBs of the quantizer fractional output and at least one lower order filter processing the LSBs of the quantizer fractional output. The outputs of these filters are then combined with the input through a combiner with the result being received by the quantizer. The quantizer then produces the output integer bitstream along with the fractional bitstream.

Abstract: A delta sigma modulator which employs a plurality of accumulators with non-power-of-2 modulus. The accumulators may consist of a primary non-power-of-2 modulus accumulator and a secondary non-power-of-2 modulus accumulator. The number of bits in the primary accumulators affects the frequency resolution of the resultant delta sigma fractional N frequency synthesizer and can be the minimum number of bits required by the resolution specification. The secondary accumulator integrates the carry outputs of its corresponding primary accumulators. This integration results in attenuating the dc content of the modulator output by a factor equal to the modulus of the secondary accumulators and may require compensation in the recombination block.

Abstract: A delta sigma modulator which employs a plurality of accumulators with non-power-of-2 modulus. The accumulators may consist of a primary non-power-of-2 modulus accumulator and a secondary non-power-of-2 modulus accumulator. The number of bits in the primary accumulators affects the frequency resolution of the resultant delta sigma fractional N frequency synthesizer and can be the minimum number of bits required by the resolution specification. The secondary accumulator integrates the carry outputs of its corresponding primary accumulators. This integration results in attenuating the dc content of the modulator output by a factor equal to the modulus of the secondary accumulators and may require compensation in the recombination block.

Abstract: Methods and devices for an improved delta sigma modulator. The delta sigma modulator has multiple filters with at least one high order filter processing the MSBs of the quantizer fractional output and at least one lower order filter processing the LSBs of the quantizer fractional output. The outputs of these filters are then combined with the input through a combiner with the result being received by the quantizer. The quantizer then produces the output integer bitstream along with the fractional bitstream.

Abstract: Methods, systems and components for use with or as a phase frequency detector. The phase frequency detector stretches its output pulse, allowing the detector to operate in a more linear region. As part of the invention, a new configuration for a D type flip flop is also disclosed. In one embodiment, the D type flip flop triggers at both the rising and the falling edges of the reference input, allowing a lower frequency input to be used while having the advantages of a higher frequency.

Abstract: A complex valued delta sigma Phase Locked Loop (PLL) demodulator. The demodulator is a multiple stage demodulator. The first stage is a conversion stage which converts an incoming signal into a first complex representation. The second stage is a direct digital synthesizer (DDS)/mixer which synthesizes a signal to be mixed with the first complex signal and performs the mixing operation to produce a second complex output. This second complex signal is controlled by a bitstream fed back from the third stage—a phase quantizer stage. The bitstream represents the quantized phase difference between the synthesized signal and the first complex signal. The DDS/mixer stage then measures the synthesized signal for any phase difference from the incoming signal through the feedback inherent to a PLL, the bitstream thus provides an output that gives the frequency of the desired signal. As a side benefit, the real component of the second complex signal, provides an amplitude estimate of the desired signal.