Patents by Inventor Tomás Apostol Palacios
Tomás Apostol Palacios has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10871466Abstract: A sensor device including a substrate that is transparent and/or flexible, and a transparent sensor array disposed on the substrate. The transparent sensor array includes transparent sensor circuits and transparent interconnects electrically coupled to the transparent sensor circuits. Each of the transparent sensor circuits includes a transparent transistor. A transparent slide may include a transparent sensor circuit disposed on a transparent substrate. The slide may be prepared for observation of a specimen by placing the specimen in fluidic communication with the transparent sensor circuit. A flexible sensor device may include an array of transparent sensor circuits disposed on a flexible substrate. The flexible sensor device may be placed on the surface of an object to determine parameters at locations adjacent to the surface of the object. A method of fabricating an integrated circuit may include using a multilayer etch mask of electron-beam resist and photoresist.Type: GrantFiled: November 4, 2016Date of Patent: December 22, 2020Assignee: Massachusetts Institute of TechnologyInventors: Charles E. Mackin, Tomás Apostol Palacios
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Patent number: 10439059Abstract: A transistor includes a first gate-controlled region having a first threshold voltage and a second gate-controlled region in parallel with the first gate-controlled region. The second gate-controlled region has a second threshold voltage different form the first threshold voltage.Type: GrantFiled: December 20, 2017Date of Patent: October 8, 2019Assignee: Massachusetts Institute of TechnologyInventors: Tomas Apostol Palacios, Sameer Jayanta-Joglekar, Ujwal Radhakrishna
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Patent number: 10297456Abstract: A dielectric structure for a nitride semiconductor device and a method of forming the same. A semiconductor device includes at least one semiconductor layer. The at least one semiconductor layer includes a gallium nitride semiconductor material. The semiconductor device also includes an oxidized layer disposed over the at least one semiconductor layer. The oxidized layer includes an oxidized form of the gallium nitride semiconductor of the at least one semiconductor layer. A silicon oxide layer is disposed over the oxidized layer. A gate is disposed over the silicon oxide layer.Type: GrantFiled: March 29, 2017Date of Patent: May 21, 2019Assignee: Massachusetts Institute of TechnologyInventors: Bernard A. Alamariu, Omair I. Saadat, Tomas Apostol Palacios
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Patent number: 10256352Abstract: A vertical semiconductor transistor and a method of forming the same. A vertical semiconductor transistor has at least one semiconductor region, a source, and at least one gate region. The at least one semiconductor region includes a III-nitride semiconductor material. The source is formed over the at least one semiconductor region. The at least one gate region is formed around at least a portion of the at least one semiconductor region.Type: GrantFiled: December 22, 2016Date of Patent: April 9, 2019Assignee: Massachusetts Institute of TechnologyInventors: Min Sun, Tomas Apostol Palacios
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Publication number: 20180321184Abstract: A sensor device including a substrate that is transparent and/or flexible, and a transparent sensor array disposed on the substrate. The transparent sensor array includes transparent sensor circuits and transparent interconnects electrically coupled to the transparent sensor circuits. Each of the transparent sensor circuits includes a transparent transistor. A transparent slide may include a transparent sensor circuit disposed on a transparent substrate. The slide may be prepared for observation of a specimen by placing the specimen in fluidic communication with the transparent sensor circuit. A flexible sensor device may include an array of transparent sensor circuits disposed on a flexible substrate. The flexible sensor device may be placed on the surface of an object to determine parameters at locations adjacent to the surface of the object. A method of fabricating an integrated circuit may include using a multilayer etch mask of electron-beam resist and photoresist.Type: ApplicationFiled: November 4, 2016Publication date: November 8, 2018Inventors: Charles E. Mackin, Tomás Apostol Palacios
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Publication number: 20180197999Abstract: A transistor includes a first gate-controlled region having a first threshold voltage and a second gate-controlled region in parallel with the first gate-controlled region. The second gate-controlled region has a second threshold voltage different form the first threshold voltage.Type: ApplicationFiled: December 20, 2017Publication date: July 12, 2018Applicant: Massachusetts Institute of TechnologyInventors: Tomas Apostol Palacios, Sameer Jayanta-Joglekar, Ujwal Radhakrishna
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Patent number: 9911813Abstract: A semiconductor device includes a first region having a first semiconductor material and a second region having a second semiconductor material. The second region is formed over the first region. The semiconductor device also includes a current blocking structure formed in the first region between first and second terminals of the semiconductor device. The current blocking structure is configured to reduce current flow in the first region between the first and second terminals.Type: GrantFiled: December 11, 2013Date of Patent: March 6, 2018Assignee: Massachusetts Institute of TechnologyInventors: Bin Lu, Elison de Nazareth Matioli, Tomas Apostol Palacios
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Publication number: 20170301546Abstract: A dielectric structure for a nitride semiconductor device and a method of forming the same. A semiconductor device includes at least one semiconductor layer. The at least one semiconductor layer includes a gallium nitride semiconductor material. The semiconductor device also includes an oxidized layer disposed over the at least one semiconductor layer. The oxidized layer includes an oxidized form of the gallium nitride semiconductor of the at least one semiconductor layer. A silicon oxide layer is disposed over the oxidized layer. A gate is disposed over the silicon oxide layer.Type: ApplicationFiled: March 29, 2017Publication date: October 19, 2017Applicant: Massachusetts Institute of TechnologyInventors: Bernard A. Alamariu, Omair I. Saadat, Tomas Apostol Palacios
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Publication number: 20170236951Abstract: A vertical semiconductor transistor and a method of forming the same. A vertical semiconductor transistor has at least one semiconductor region, a source, and at least one gate region. The at least one semiconductor region includes a III-nitride semiconductor material. The source is formed over the at least one semiconductor region. The at least one gate region is formed around at least a portion of the at least one semiconductor region.Type: ApplicationFiled: December 22, 2016Publication date: August 17, 2017Applicant: Massachusetts Institute of TechnologyInventors: Min Sun, Tomas Apostol Palacios
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Patent number: 9711594Abstract: A field effect transistor that has a source, a drain, a gate and a semiconductor region. The semiconductor region has a source access region between the gate and the source, a drain access region between the gate and the drain, and a channel region under the gate. The channel region under the gate has a maximum current-carrying capability that is lower than a maximum current-carrying capability of the source access region.Type: GrantFiled: August 28, 2015Date of Patent: July 18, 2017Assignee: Massachusetts Institute of TechnologyInventors: Dong Seup Lee, Tomas Apostol Palacios
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Patent number: 9704959Abstract: A field effect transistor that has a source, a drain, a gate, a semiconductor region, and a dielectric region. The dielectric region is located between the semiconductor region and the gate. Negatively charged ions are located within the dielectric layer underneath the gate.Type: GrantFiled: May 21, 2014Date of Patent: July 11, 2017Assignee: Massachusetts Institute of TechnologyInventors: Yuhao Zhang, Tomas Apostol Palacios
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Patent number: 9634111Abstract: A method of protecting a semiconductor structure from water and a semiconductor structure formed by the method. The semiconductor structure includes a wide-bandgap semiconductor material in which at least one semiconductor device is formed. The method includes heating the semiconductor structure in a vacuum to a temperature of at least 200° C. to remove water from the semiconductor structure. The method also includes, after the heating of the semiconductor structure, forming a layer comprising a hydrophobic material over the semiconductor structure. The semiconductor structure is kept in the vacuum between the heating of the semiconductor structure and the forming of the layer comprising the hydrophobic material.Type: GrantFiled: April 23, 2013Date of Patent: April 25, 2017Assignee: Massachusetts Institute of TechnologyInventors: Feng Gao, Di Chen, Bin Lu, Tomas Apostol Palacios
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Patent number: 9570600Abstract: A semiconductor structure has a first layer that includes a first semiconductor material and a second layer that includes a second semiconductor material. The first semiconductor material is selectively etchable over the second semiconductor material using a first etching process. The first layer is disposed over the second layer. A recess is disposed at least in the first layer. Also described is a method of forming a semiconductor structure that includes a recess. The method includes etching a region in a first layer using a first etching process. The first layer includes a first semiconductor material. The first etching process stops at a second layer beneath the first layer. The second layer includes a second semiconductor material.Type: GrantFiled: November 15, 2013Date of Patent: February 14, 2017Assignee: Massachusetts Institute of TechnologyInventors: Bin Lu, Min Sun, Tomas Apostol Palacios
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Publication number: 20160133710Abstract: A semiconductor device includes a first region having a first semiconductor material and a second region having a second semiconductor material. The second region is formed over the first region. The semiconductor device also includes a current blocking structure formed in the first region between first and second terminals of the semiconductor device. The current blocking structure is configured to reduce current flow in the first region between the first and second terminals.Type: ApplicationFiled: December 11, 2013Publication date: May 12, 2016Applicant: Massachusetts Institute of TechnologyInventors: Bin Lu, Alison de Nazareth Matioli, Tomas Apostol Palacios
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Patent number: 9337301Abstract: Semiconductor structures and techniques are described which enable forming aluminum nitride (AIN) based devices by confining carriers in a region of AIN by exploiting the polar nature of AIN materials. Embodiments of AIN transistors utilizing polarization-based carrier confinement are described.Type: GrantFiled: December 21, 2012Date of Patent: May 10, 2016Assignee: Massachusetts Institute of TechnologyInventors: Tomas Apostol Palacios, Tatsuya Fujishima
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Patent number: 9293538Abstract: An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance.Type: GrantFiled: November 18, 2013Date of Patent: March 22, 2016Assignee: Massachusetts Institute of TechnologyInventors: Tomas Apostol Palacios, Bin Lu, Elison de Nazareth Matioli
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Publication number: 20150372081Abstract: A field effect transistor that has a source, a drain, a gate and a semiconductor region. The semiconductor region has a source access region between the gate and the source, a drain access region between the gate and the drain, and a channel region under the gate. The channel region under the gate has a maximum current-carrying capability that is lower than a maximum current-carrying capability of the source access region.Type: ApplicationFiled: August 28, 2015Publication date: December 24, 2015Applicant: Massachusetts Institute of TechnologyInventors: Dong Seup Lee, Tomas Apostol Palacios
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Publication number: 20150318360Abstract: A semiconductor device includes a first region having a first semiconductor material and a second region having a second semiconductor material. The second region is formed over the first region. The semiconductor device also includes a current blocking structure formed in the first region between first and second terminals of the semiconductor device. The current blocking structure is configured to reduce current flow in the first region between the first and second terminals.Type: ApplicationFiled: December 11, 2013Publication date: November 5, 2015Applicant: Massachusetts Institute of TechnologyInventors: Bin Lu, Alison de Nazareth Matioli, Tomas Apostol Palacios
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Publication number: 20150270356Abstract: A vertical semiconductor device and a method of forming the same. A vertical semiconductor device has a substrate that includes a first material, a first electrode below the substrate, and at least one semiconductor region. The at least one semiconductor region includes a second material different from the first material. The second material is a III-nitride semiconductor material. The at least one semiconductor region is formed over the substrate. The vertical semiconductor device also has a second electrode over the at least one semiconductor region.Type: ApplicationFiled: March 19, 2015Publication date: September 24, 2015Applicant: Massachusetts Institute of TechnologyInventors: Tomas Apostol Palacios, Yuhao Zhang
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Patent number: 9041003Abstract: An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance.Type: GrantFiled: October 11, 2012Date of Patent: May 26, 2015Assignee: Massachusetts Institute of TechnologyInventors: Tomas Apostol Palacios, Bin Lu, Elison de Nazareth Matioli