Abstract: The present disclosure relates generally to static random-access memory (SRAM) devices. Specifically, the disclosure proposes a SRAM device with a three-layered SRAM cell design. The SRAM cell comprises a storage comprising four storage transistors, and comprises two access transistors to control access to the storage cell. The SRAM cell further comprises a stack of three layer structures. Two of the storage transistors are formed in a first layer structure of the stack, and two other of the storage transistors are formed in a second layer structure of the stack adjacent to the first layer structure. The two access transistors are formed in a third layer structure of the stack adjacent to the second layer structure. Each layer structure comprises a semiconductor material, the transistors in the layer structure are based on that semiconductor material, and at least two of the three layer structures comprise a different type of semiconductor material.

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set.

Abstract: A method for manufacturing a dual work function semiconductor device includes forming a first silicon oxide layer on a substrate and forming a first hafnium-containing dielectric material layer on the first silicon oxide layer. The method further includes forming an aluminum-containing dielectric material layer on the first hafnium-containing dielectric material layer and performing a thermal treatment to intermix the silicon oxide layer, the first hafnium-containing dielectric material layer and the aluminum-containing dielectric material layers. This results in an intermixing dielectric layer containing hafnium, aluminum, silicon, and oxygen. The method further includes forming a first metal-containing conductive layer on the intermixing dielectric layer and patterning the first metal-containing conductive layer and the intermixing dielectric layer, thereby forming a first gate stack in a first region.

Abstract: The disclosed technology generally relates to integrated circuit devices and methods of forming the same, and more particularly to metal electrodes whose effective work function can be tuned. In one aspect, a method of forming a metal electrode of a semiconductor structure includes providing a semiconductor substrate having at least a region covered with a dielectric. The semiconductor substrate is introduced into a chamber configured for atomic layer deposition (ALD). A metal for the metal electrode is deposited at least on the dielectric by performing an ALD cycle. Performing the ALD cycle includes pulsing a Ti-containing precursor gas followed by pulsing a Ta-containing precursor gas, and further includes pulsing NH3 gas.

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set.

Abstract: A method for manufacturing a dual work function semiconductor device includes forming a first silicon oxide layer on a substrate and forming a first hafnium-containing dielectric material layer on the first silicon oxide layer. The method further includes forming an aluminum-containing dielectric material layer on the first hafnium-containing dielectric material layer and performing a thermal treatment to intermix the silicon oxide layer, the first hafnium-containing dielectric material layer and the aluminum-containing dielectric material layers. This results in an intermixing dielectric layer containing hafnium, aluminum, silicon, and oxygen. The method further includes forming a first metal-containing conductive layer on the intermixing dielectric layer and patterning the first metal-containing conductive layer and the intermixing dielectric layer, thereby forming a first gate stack in a first region.

Abstract: The disclosed technology generally relates to integrated circuit devices and methods of forming the same, and more particularly to metal electrodes whose effective work function can be tuned. In one aspect, a method of forming a metal electrode of a semiconductor structure includes providing a semiconductor substrate having at least a region covered with a dielectric. The semiconductor substrate is introduced into a chamber configured for atomic layer deposition (ALD). A metal for the metal electrode is deposited at least on the dielectric by performing an ALD cycle. Performing the ALD cycle includes pulsing a Ti-containing precursor gas followed by pulsing a Ta-containing precursor gas, and further includes pulsing NH3 gas.

Abstract: The disclosed technology generally relates a semiconductor device comprising transistors, and more particularly to a semiconductor device comprising transistors each having a gate stack with a different effective work function, and methods of fabricating such a device. In one aspect, the method of fabricating the semiconductor comprises providing at least two channel regions in the substrate and providing a dielectric layer on the substrate. The method additionally includes forming a plurality of gate regions by providing openings in the dielectric layer. The method further includes providing a gate dielectric layer in the openings and providing on the gate dielectric layer of each of the gate regions a barrier layer stack having different thickness along the different gate regions.

Abstract: A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method includes providing a substrate having first and second areas for forming first and second transistor types. The method additionally includes forming a dielectric layer on the substrate, which extends to cover at least parts of the first and second areas. The method additionally includes forming a first metal layer/stack on the dielectric layer in the first area, where the first metal layer/stack comprises a first work function-shifting element. The method additionally includes forming a second metal layer/stack on the first metal layer in the first area and on the dielectric layer in the second area, where the second metal layer/stack comprises a second work function-shifting element.

Abstract: The disclosed technology generally relates a semiconductor device comprising transistors, and more particularly to a semiconductor device comprising transistors each having a gate stack with a different effective work function, and methods of fabricating such a device. In one aspect, the method of fabricating the semiconductor comprises providing at least two channel regions in the substrate and providing a dielectric layer on the substrate. The method additionally includes forming a plurality of gate regions by providing openings in the dielectric layer. The method further includes providing a gate dielectric layer in the openings and providing on the gate dielectric layer of each of the gate regions a barrier layer stack having different thickness along the different gate regions.

Abstract: A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method includes providing a substrate having first and second areas for forming first and second transistor types. The method additionally includes forming a dielectric layer on the substrate, which extends to cover at least parts of the first and second areas. The method additionally includes forming a first metal layer/stack on the dielectric layer in the first area, where the first metal layer/stack comprises a first work function-shifting element. The method additionally includes forming a second metal layer/stack on the first metal layer in the first area and on the dielectric layer in the second area, where the second metal layer/stack comprises a second work function-shifting element.

Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.

Abstract: A substrate treating method comprising a step of preparing a semiconductor substrate (W, 11) which has an oxide film (13, 14) containing at least one of a rare earth oxide and an alkaline earth oxide, at least a portion of the oxide film (13, 14) being exposed, and a rinse step of supplying the oxide film (13, 14) on the semiconductor substrate (W, 11) with a rinse liquid made of an alkaline chemical or an organic solvent. Preferably, the alkaline chemical is an alkaline aqueous solution having a pH of more than 7. Further, preferably, the organic solvent is a high concentration organic solvent having a concentration of substantially 100%.

Abstract: One inventive aspect relates to a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus about 10%. The method further comprises thinning the high-k dielectric layer to a second thickness. Another inventive aspect relates to a semiconductor device comprising a high-k dielectric layer as fabricated by the method.

Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.

Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.

Abstract: A substrate treating method comprising a step of preparing a semiconductor substrate (W, 11) which has an oxide film (13, 14) containing at least one of a rare earth oxide and an alkaline earth oxide, at least a portion of the oxide film (13, 14) being exposed, and a rinse step of supplying the oxide film (13, 14) on the semiconductor substrate (W, 11) with a rinse liquid made of an alkaline chemical or an organic solvent. Preferably, the alkaline chemical is an alkaline aqueous solution having a pH of more than 7. Further, preferably, the organic solvent is a high concentration organic solvent having a concentration of substantially 100%.

Abstract: A method for manufacturing a dual work function device is disclosed. In one aspect, the process includes a first and second region in a substrate. The method includes forming a first transistor in the first region which has a first work function. Subsequently, a second transistor is formed in the second region having a different work function. The process of forming the first transistor includes providing a first gate dielectric stack having a first gate dielectric layer and a first gate dielectric capping layer on the first gate dielectric layer, performing a thermal treatment to modify the first gate dielectric stack, the modified first gate dielectric stack defining the first work function, providing a first metal gate electrode layer on the modified first gate dielectric stack, and patterning the first metal gate electrode layer and the modified first gate dielectric stack.

Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.

Abstract: A new MOSFET device is described comprising a metal gate electrode, a gate dielectric and an interfacial layer. The interfacial layer comprises a lanthanum hafnium oxide material for modulating the effective work function of the metal gate. The gate dielectric material in contact with the interfacial layer is different that the interfacial layer material. A method for its manufacture is also provided and its applications.