Abstract: A layered thin film device, such as a MTJ (Magnetic Tunnel Junction) device can be customized in shape by sequentially forming its successive layers over a symmetrically curved electrode. By initially shaping the electrode to have a concave or convex surface, the sequentially formed layers conform to that shape and acquire it and are subject to stresses that cause various crystal defects to migrate away from the axis of symmetry, leaving the region immediately surrounding the axis of symmetry relatively defect free. The resulting stack can then be patterned to leave only the region that is relatively defect free.

Abstract: Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies.

Abstract: Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies.

Abstract: Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies.

Abstract: Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies.

Abstract: Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies.

Abstract: Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies.

Abstract: A method and apparatus that coordinates refresh and parity-scanning in DRAM-based devices such that parity-scan operations substitute for refresh operations when both operations are required in the system. The process of parity-scanning automatically refreshes the entries being scanned, subject to refresh and parity-scan interval requirements. As such, refresh and parity-scan operations may be performed in a single operation, which bolsters the scheduling and performance of the two operations.

Abstract: A method and apparatus that coordinates refresh and parity-scanning in DRAM-based devices such that parity-scan operations substitute for refresh operations when both operations are required in the system. The process of parity-scanning automatically refreshes tie entries being scanned, subject to refresh and parity-scan interval requirements. As such, refresh and parity-scan operations may be performed in a single operation, which bolsters the scheduling and performance of the two operations.

Abstract: A method and apparatus that coordinates refresh and parity-scanning in DRAM-based devices such that parity-scan operations substitute for refresh operations when both operations are required in the system. The process of parity-scanning automatically refreshes the entries being scanned, subject to refresh and parity-scan interval requirements. As such, refresh and parity-scan operations may be performed in a single operation, which bolsters the scheduling and performance of the two operations.

Abstract: A method and apparatus that coordinates refresh and parity-scanning in DRAM-based devices such that parity-scan operations substitute for refresh operations when both operations are required in the system. The process of parity-scanning automatically refreshes the entries being scanned, subject to refresh and parity-scan interval requirements. As such, refresh and parity-scan operations may be performed in a single operation, which bolsters the scheduling and performance of the two operations.

Abstract: Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies.

Abstract: Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies.

Abstract: A method and apparatus that coordinates refresh and parity-scanning in DRAM-based devices such that parity-scan operations substitute for refresh operations when both operations are required in the system. The process of parity-scanning automatically refreshes the entries being scanned, subject to refresh and parity-scan interval requirements. As such, refresh and parity-scan operations may be performed in a single operation, which bolsters the scheduling and performance of the two operations.

Abstract: Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies.

Abstract: A method and apparatus that coordinates refresh and parity-scanning in DRAM-based devices such that parity-scan operations substitute for refresh operations when both operations are required in the system. The process of parity-scanning automatically refreshes the entries being scanned, subject to refresh and parity-scan interval requirements. As such, refresh and parity-scan operations may be performed in a single operation, which bolsters the scheduling and performance of the two operations.