Abstract: A packaging substrate and a method for mounting an integrated circuit and/or a circuit component is presented. The packaging substrate includes an upper surface for mounting the integrated circuit and/or circuit component; a lower surface opposite to the upper surface, wherein the lower surface is for mounting to a printed circuit board (PCB); a non-conductive material; wherein the non-conductive material is a plastic: an inductor structure at least partially embedded in the non-conductive material; first and second conductive materials, and conductive pillars, arranged to form a first coil and a second coil having an inductance; wherein the first coil and second coil are arranged as a toroid transformer wound in a double helix configuration.

Abstract: Improved techniques for sensing and reporting power consumption from a single or multiple power supplies are disclosed. The disclosed techniques comprise integrated circuit solutions for sensing power. In some embodiments, an integrated circuit comprises circuitry for converting source voltage into a pulse-width modulation (PWM) signal and circuitry for modulating the PWM signal with a current sense signal to determine sensed power.

Abstract: A packaging substrate and a method for mounting an integrated circuit and/or a circuit component is presented. The packaging substrate has an upper surface for mounting the integrated circuit and/or circuit component, a non-conductive material, an inductor structure at least partially embedded in the non-conductive material. The inductor structure has i) a first conductive material at least partially on a first layer, ii) a second conductive material at least partially on a second layer, and iii) a plurality of conductive pillars, wherein the first conductive material, the second conductive material and the conductive pillars are arranged to form a first coil having an inductance. The first coil is arranged as one of a) a solenoid having an axis that is approximately parallel to the upper surface of the packaging substrate, and b) a toroid.

Abstract: A technique for enhancing the conduction of a p-channel device is disclosed. Specifically, a negative charge pump is configured to provide a gate drive voltage to a p-channel device. The negative charge pump creates a negative voltage potential below ground and facilitates increased gate drive for the p-channel device. The gate drive voltage output by the negative charge pump may be selected such that it is optimal for the p-channel device operation.

Abstract: In a typical DC-DC converter, an error amplifier is used to sense and amplify the difference between the feedback voltage and the reference voltage. In the event of current overloading (limit condition), example embodiments of the disclosed systems and methods of over-load protection with voltage fold-back fold back the reference voltage proportional to the current limit. The regulator may continue to regulate in this fold-back voltage reference condition without shutting down the converter, saturating the inductor, or causing a catastrophic failure at the power FETs. The disclosed systems and methods of over-load protection with voltage fold-back resolve consecutive switching cycle current build up in high input voltage DC/DC convertor applications due to the latency of current limit circuitry.

Abstract: Improved techniques for sensing and reporting consumed power are disclosed. The disclosed techniques comprise an integrated circuit solution for sensing power. In some embodiments, such an integrated circuit comprises a resistor on which a sense voltage sensed across an external resistor in response to a load current is mirrored and an analog-to-digital converter configured to regulate the voltage across the resistor and output a binary value representing power. The binary value representing power may integrate one or more electrical or environmental parameters such as current, voltage, temperature, battery voltage, etc.

Abstract: In a typical DC-DC converter, an error amplifier is used to sense and amplify the difference between the feedback voltage and the reference voltage. In the event of current overloading (limit condition), example embodiments of the disclosed systems and methods of over-load protection with voltage fold-back fold back the reference voltage proportional to the current limit. The regulator may continue to regulate in this fold-back voltage reference condition without shutting down the converter, saturating the inductor, or causing a catastrophic failure at the power FETs. The disclosed systems and methods of over-load protection with voltage fold-back resolve consecutive switching cycle current build up in high input voltage DC/DC convertor applications due to the latency of current limit circuitry.

Abstract: The present application relates to a method of fabricating planar circuits using a photo lithographic mask set, to the photo lithographic mask set, and to a planar circuit fabricated with the photo lithographic mask set. The instant invention involves separating a photo lithographic mask into two parts, namely, a master mask and one or more slave masks. The master mask and the one or more slave masks form a photo lithographic mask set that is used iteratively to fabricate the planar circuits. In particular, the master mask is used as a template to provide the general layout for the planar circuit, while each slave mask is varied to tune and/or tailor the planar circuit. Since only a small portion of the planar circuit is redesigned and/or rewritten as a new mask (i.e., the slave mask), the instant invention provides a simple and cost effective method for optimizing planar circuits.

Abstract: The present application relates to a method of fabricating planar circuits using a photolithographic mask set, to the photolithographic mask set, and to a planar circuit fabricated with the photolithographic mask set. The instant invention involves separating a photolithographic mask into two parts, namely, a master mask and one or more slave masks. The master mask and the one or more slave masks form a photolithographic mask set that is used iteratively to fabricate the planar circuits. In particular, the master mask is used as a template to provide the general layout for the planar circuit, while each slave mask is varied to tune and/or tailor the planar circuit. Since only a small portion of the planar circuit is redesigned and/or rewritten as a new mask (i.e., the slave mask), the instant invention provides a simple and cost effective method for optimizing planar circuits.