Patents by Inventor Tom V. Geukens

Tom V. Geukens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250199703
    Abstract: Apparatuses and methods for read source determination are provided. One example apparatus can include a controller configured to determine a source for read requests and to direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount, and direct read requests for the first portion of data to a first block of quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount.
    Type: Application
    Filed: February 25, 2025
    Publication date: June 19, 2025
    Inventors: Tom V. Geukens, Byron D. Harris
  • Patent number: 12260101
    Abstract: Apparatuses and methods for read source determination are provided. One example apparatus can include a controller configured to determine a source for read requests and to direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount, and direct read requests for the first portion of data to a first block of quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Tom V. Geukens, Byron D. Harris
  • Publication number: 20240330177
    Abstract: Aspects of the present disclosure configure a memory sub-system controller to fold data based on valid translational unit count (VTC) values in a memory sub-system. The controller receives a request to perform a folding operation on data stored in an individual block stripe of the set of memory components. The controller retrieves, from a VTC table, a plurality of VTC values corresponding to a plurality of portions of the individual block stripe. The controller compares a first VTC value of the plurality of VTC values associated with a first of the plurality of portions to a second VTC value of the plurality of VTC values associated with a second of the plurality of portions. The controller performs the folding operation on a subset of the plurality of portions based on a result of comparing the first VTC value to the second VTC value.
    Type: Application
    Filed: March 25, 2024
    Publication date: October 3, 2024
    Inventors: Meng Wei, Tom V. Geukens
  • Publication number: 20240231693
    Abstract: Apparatuses and methods for determining performing write operations on a number of planes are provided. One example apparatus can include a controller configured to associate a first number of blocks together, wherein each of the first number of blocks are each located on different planes, receive commands to write data to a first page on the number of first blocks, and write data to the first page of each of the first number of blocks during a first time period.
    Type: Application
    Filed: October 17, 2023
    Publication date: July 11, 2024
    Inventors: Tom V. Geukens, John J. Kane
  • Publication number: 20240231660
    Abstract: Apparatuses and methods for read source determination are provided. One example apparatus can include a controller configured to determine a source for read requests and to direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount, and direct read requests for the first portion of data to a first block of quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount.
    Type: Application
    Filed: September 29, 2023
    Publication date: July 11, 2024
    Inventors: Tom V. Geukens, Byron D. Harris
  • Publication number: 20240134551
    Abstract: Apparatuses and methods for read source determination are provided. One example apparatus can include a controller configured to determine a source for read requests and to direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount, and direct read requests for the first portion of data to a first block of quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 25, 2024
    Inventors: Tom V. Geukens, Byron D. Harris
  • Publication number: 20240134570
    Abstract: Apparatuses and methods for determining performing write operations on a number of planes are provided. One example apparatus can include a controller configured to associate a first number of blocks together, wherein each of the first number of blocks are each located on different planes, receive commands to write data to a first page on the number of first blocks, and write data to the first page of each of the first number of blocks during a first time period.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 25, 2024
    Inventors: Tom V. Geukens, John J. Kane
  • Patent number: 11726716
    Abstract: Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventors: John Traver, Ning Zhao, Tom V. Geukens, Yun Li
  • Patent number: 11698746
    Abstract: An operation performed on a non-volatile memory device is detected. A type of the operation is determined. The type of the operation comprises a type identifier and a type modifier. A journal entry is generated reflecting the operation. The journal entry comprises a body reflecting the operation and a header comprising the type identifier and the type modifier. A combination of the type identifier and the type modifier define a size of the journal entry. The journal entry is written to a volatile memory device.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: July 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Tom V Geukens, Daniel A Boals
  • Patent number: 11221776
    Abstract: Methods, systems, and devices for metadata indication are described herein. A method includes receiving, from a host system, a read command to retrieve information from a first block of a memory device, identifying a transfer unit associated with the first block indicated in the read command, identifying an indicator in metadata of the identified transfer unit indicating that at least one sector of the transfer unit has been altered based at least in part on identifying the transfer unit, validating data of the transfer unit stored in the memory device based at least in part on identifying the indicator in the metadata, and retrieving the information stored in the first block based at least in part on validating the data of the transfer unit.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: January 11, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Mark Ish, Yiran Liu, Tom V. Geukens
  • Publication number: 20210405929
    Abstract: Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.
    Type: Application
    Filed: September 8, 2021
    Publication date: December 30, 2021
    Inventors: John Traver, Ning Zhao, Tom V. Geukens, Yun LI
  • Patent number: 11137943
    Abstract: Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John Traver, Ning Zhao, Tom V. Geukens, Yun Li
  • Publication number: 20210278995
    Abstract: Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 9, 2021
    Inventors: John Traver, Ning Zhao, Tom V. Geukens, Yun Li
  • Publication number: 20210200436
    Abstract: Methods, systems, and devices for metadata indication are described herein. A method includes receiving, from a host system, a read command to retrieve information from a first block of a memory device, identifying a transfer unit associated with the first block indicated in the read command, identifying an indicator in metadata of the identified transfer unit indicating that at least one sector of the transfer unit has been altered based at least in part on identifying the transfer unit, validating data of the transfer unit stored in the memory device based at least in part on identifying the indicator in the metadata, and retrieving the information stored in the first block based at least in part on validating the data of the transfer unit.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Inventors: Mark Ish, Yiran Liu, Tom V. Geukens