Abstract: A circuit and method for producing a walking one pattern in a shift register. The circuit comprises a shift register and a NOR gate. The NOR gate output is connected to the data input of the shift register, and the data output of each of said register stages is connected to a respective one of the NOR gate inputs.

Abstract: A matrix display maintains synchronization with an input NTSC composite video signal by combining the functions of a phase locked loop, a column selector, and a row selector. The matrix includes display cells arranged in rows and columns, each display cell enabled for display on receipt of a column pointer signal and a row pointer signal. The column selector includes a shift circuit that shifts a walking-one pattern to assert in turn one column pointer signal at a time for each column in the matrix. An overflow signal from the shift circuit is used for three functions: (1) to reinstate the walking pattern in the column selector, (2) to lock the phase locked loop on the horizontal synchronization pulse of the NTSC signal, (3) to clock the row selector. The row selector includes a shift circuit and walking-one pattern to assert in turn one row pointer signal for each row of the matrix.

Abstract: A serial to parallel conversion circuit uses a dynamic shift register in a phase locked loop for an index to access a parallel holding register. The composite input signal includes serial data to be sampled and a synchronizing signal at an integer factor of the sampling serial data rate. The phase locked loop generates a control signal for sampling the serial data at a multiple of the synchronizing frequency by incorporating a delay between a variable frequency oscillator output and a phase comparator input. The delay element in one embodiment includes a shift register with a walking-one pattern that overflows to the phase comparator. The walking-one pattern is used to identify which position of the holding register should store the next sample of the input signal. The shift register is self-initialized by a logic combination of all shift register outputs. Power dissipation by the serial to parallel conversion circuit is minimal because only one 7-transistor shift register cell draws current at a time.

Abstract: A matrix display maintains synchronization with an input NTSC composite video signal by combining the functions of a phase locked loop, a column selector, and a row selector. The matrix includes display cells arranged in rows and columns, each display cell enabled for display on receipt of a column pointer signal and a row pointer signal. The column selector includes a shift circuit that shifts a walking-one pattern to assert in turn one column pointer signal at a time for each column in the matrix. An overflow signal from the shift circuit is used for three functions: (1) to reinstate the walking pattern in the column selector, (2) to lock the phase locked loop on the horizontal synchronization pulse of the NTSC signal, (3) to clock the row selector. The row selector includes a shift circuit and walking-one pattern to assert in turn one row pointer signal for each row of the matrix.

Abstract: A serial to parallel conversion circuit uses a dynamic shift register in a phase locked loop for an index to access a parallel holding register. The composite input signal includes serial data to be sampled and a synchronizing signal at an integer factor of the sampling serial data rate. The phase locked loop generates a control signal for sampling the serial data at a multiple of the synchronizing frequency by incorporating a delay between a variable frequency oscillator output and a phase comparator input. The delay element in one embodiment includes a shift register with a walking-one pattern that overflows to the phase comparator. The walking-one pattern is used to identify which position of the holding register should store the next sample of the input signal. The shift register is self-initialized by a logic combination of all shift register outputs. Power dissipation by the serial to parallel conversion circuit is minimal because only one 7-transistor shift register cell draws current at a time.