Abstract: Testing of integrated circuitry, wherein the integrated circuitry includes a flip-flop with an asynchronous input, so that during performance of asynchronous scan patterns, glitches are avoided. Combinatorial logic circuitry delivers a local reset signal to the asynchronous input independent of an assertion of an asynchronous global reset signal. A synchronous scan test is performed of delivery of the local reset signal from the combinatorial logic circuitry while masking delivery of any reset signal to the asynchronous input of the flip-flop. An asynchronous scan test is performed of an asynchronous reset of the flip-flop with the asynchronous global reset signal while masking delivery of the local reset signal to the asynchronous input of the flip-flop.

Abstract: Testing of integrated circuitry, wherein the integrated circuitry includes a flip-flop with an asynchronous input, so that during performance of asynchronous scan patterns, glitches are avoided. Combinatorial logic circuitry delivers a local reset signal to the asynchronous input independent of an assertion of an asynchronous global reset signal. A synchronous scan test is performed of delivery of the local reset signal from the combinatorial logic circuitry while masking delivery of any reset signal to the asynchronous input of the flip-flop. An asynchronous scan test is performed of an asynchronous reset of the flip-flop with the asynchronous global reset signal while masking delivery of the local reset signal to the asynchronous input of the flip-flop.

Abstract: Certain aspects of the disclosure are directed toward test control and test access configuration via two pins on an integrated circuit (IC). According to a specific example, an IC chip-based apparatus is used in connection with a controller for testing a target IC. The IC chip-based apparatus includes an event (capture) circuit configured and arranged to control logic states through which a static test configuration is selected for a given event detected in response to a clock signal and to a data signal respectively derived from the controller. A test-operation control circuit may be configured and arranged to test the target IC by selectively configuring each of the clock pin and the I/O pin of the controller for use as an analog test bus, data input to the controller or data output from the controller, and carrying out dynamic operations by communicating test signals via pins of the target IC.

Abstract: Various exemplary embodiments relate to an integrated circuit device that includes a plurality of input/output pins, device circuitry, a first testing protocol interface connected to the device circuitry and to the plurality of input/output pins, and a second testing protocol interface connected to the device circuitry and to the same plurality of input/output pins as the first testing protocol interface. The first testing protocol interface is configured to test the device circuitry with a first testing protocol, and the second testing protocol interface is configured to test the device circuitry with a second testing protocol.

Abstract: Embodiments of methods and systems for digital circuit scan testing are described. In one embodiment, a method for scan testing a digital circuit involves testing a digital circuit using a scan chain to generate scan data and distributing the scan data over a plurality of scan output terminals using a sample and hold device.

Abstract: Embodiments of methods and systems for digital circuit scan testing are described.

Abstract: Various exemplary embodiments relate to an integrated circuit device that includes a plurality of input/output pins, device circuitry, a first testing protocol interface connected to the device circuitry and to the plurality of input/output pins, and a second testing protocol interface connected to the device circuitry and to the same plurality of input/output pins as the first testing protocol interface. The first testing protocol interface is configured to test the device circuitry with a first testing protocol, and the second testing protocol interface is configured to test the device circuitry with a second testing protocol.

Abstract: A method is provided for testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies. A test signal is provided using a clocked scan chain clocked at a test frequency (TCK). A transition is provided in a clock circuit reset signal (clockdiv_rst) which triggers the operation of a clock divider circuit (44) which derives the first and second clock signals (clk_xx, clk_yy, clk_zz) from an internal clock (40) of the integrated circuit. The first and second clock signals thus start at substantially the same time, and these are used during a test mode to perform a test of the integrated circuit. After test, the test result is output using the clocked scan chain clocked at the test frequency (TCK).

Abstract: A testing circuit has scan chain segments (62,64,60) defined between parallel inputs (wpi[0] . . . wpi[N?1]) and respective parallel outputs (wpo[0] . . . wpo[N?1]). The scan chain segments comprise a bank (62) of cells of a shift register circuit, a core scan chain portion (62), a first bypass path around the core scan chain portion (62) and a second bypass path around the bank (60) of cells of the shift register circuit. This architecture enables loading of data in parallel into the core scan chain, or into the shift register (WBR). In addition, each scan chain segment also has a series latching element (80), and this provides additional testing capability. In particular, the shifting of data between the latching elements (80) can be used to test the bypass paths while the internal or external mode testing is being carried out. This testing can thus be part of a single ATPG procedure.

Abstract: A method and apparatus for testing an integrated circuit core or circuitry external to an integrated circuit core using a testing circuit passes a test vector from a parallel input of the testing circuit along a shift register circuit. The shift register circuit is configured to bypass one or more cores not being tested and to provide the test vector to a core scan chain of the core being tested. The bypassed cores are configured such that the associated shift register circuit portion is driven to a hold mode in which storage elements of the shift register circuit portion have their outputs coupled to their inputs. This method provides holding of the shift register stages when a core is bypassed and in a test mode, and this means the shift register stages are less prone to errors resulting from changes in clock signals applied to the shift register stages.

Abstract: A shift register circuit is provided for storing instruction data for the testing of an integrated circuit core. The shift register circuit comprises a plurality of stages, each stage comprising a serial input (si) and a serial output (so) and a parallel output (wir_output) comprising one terminal of a parallel output of the shift register circuit. A first shift register storage element (32) is for storing a signal received from the serial input (si) and providing it to the serial output (so) in a scan chain mode of operation. A second parallel register storage element (38) is for storing a signal from the first shift register storage element (32) and providing it to the parallel output (wir_output) in an update mode of operation. The stage further comprises a feedback path (40) for providing an inverted version of the parallel output (wir_output) to the first shift register storage element (32) in a test mode of operation.

Abstract: A testing circuit has a shift register circuit (76) for storing instruction data for the testing of an integrated circuit core. Each stage of the shift register circuit comprises a first shift register storage element (32) for storing a signal received from a serial input (wsi) and providing it to a serial output (wso) in a scan chain mode of operation, and a second parallel register storage element (38) for storing a signal from the first shift register storage element and providing it to a parallel output in an update mode of operation. The testing circuit further comprises a multiplexer (70) for routing either a serial test input to the serial input (wsi) of the shift register circuit or an additional input (wpi[n]) into the serial input of the shift register circuit (76).

Abstract: Logic level crossings in an integrated circuit are detected. According to an example embodiment, a reset signal is provided to a flip-flop (314) as a function of a logic level of an integrated circuit. A logic level crossing condition of the integrated circuit is indicated as a function of the reset condition of the flip flop. In one implementation, the flip-flop is reset when the logic level is different than an expected logic level. In another implementation, a pair of flip-flops (414, 418) are implemented such that only one flip-flop is reset at a particular logic level; if the logic level crosses, both flip-flops are reset. The aforesaid condition of both flip-flops being reset is used to indicate the logic level crossing.

Abstract: Logic level crossings in an integrated circuit are detected. According to an example embodiment, a reset signal is provided to a flip-flop (314) as a function of a logic level of an integrated circuit. A logic level crossing condition of the integrated circuit is indicated as a function of the reset condition of the flip flop. In one implementation, the flip-flop is reset when the logic level is different than an expected logic level. In another implementation, a pair of flip-flops (414, 418) are implemented such that only one flip-flop is reset at a particular logic level; if the logic level crosses, both flip-flops are reset. The aforesaid condition of both flip-flops being reset is used to indicate the logic level crossing.

Abstract: A method is provided for testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies. A test signal is provided using a clocked scan chain clocked at a test frequency (TCK). A transition is provided in a clock circuit reset signal (clockdiv_rst) which triggers the operation of a clock divider circuit (44) which derives the first and second clock signals (clk_xx, clk_yy, clk_zz) from an internal clock (40) of the integrated circuit. The first and second clock signals thus start at substantially the same time, and these are used during a test mode to perform a test of the integrated circuit. After test, the test result is output using the clocked scan chain clocked at the test frequency (TCK).

Abstract: A testing circuit has a shift register circuit (76) for storing instruction data for the testing of an integrated circuit core. Each stage of the shift register circuit comprises a first shift register storage element (32) for storing a signal received from a serial input (wsi) and providing it to a serial output (wso) in a scan chain mode of operation, and a second parallel register storage element (38) for storing a signal from the first shift register storage element and providing it to a parallel output in an update mode of operation. The testing circuit further comprises a multiplexer (70) for routing either a serial test input to the serial input (wsi) of the shift register circuit or an additional input (wpi[n]) into the serial input of the shift register circuit (76).

Abstract: A testing circuit has scan chain segments (62,64,60) defined between parallel inputs (wpi[0] . . . wpi[N?1]) and respective parallel outputs (wpo[0] . . . wpo[N?1]). The scan chain segments comprise a bank (62) of cells of a shift register circuit, a core scan chain portion (62), a first bypass path around the core scan chain portion (62) and a second bypass path around the bank (60) of cells of the shift register circuit. This architecture enables loading of data in parallel into the core scan chain, or into the shift register (WBR). In addition, each scan chain segment also has a series latching element (80), and this provides additional testing capability. In particular, the shifting of data between the latching elements (80) can be used to test the bypass paths while the internal or external mode testing is being carried out. This testing can thus be part of a single ATPG procedure.

Abstract: A method and apparatus for testing an integrated circuit core or circuitry external to an integrated circuit core using a testing circuit passes a test vector from a parallel input of the testing circuit along a shift register circuit. The shift register circuit is configured to bypass one or more cores not being tested and to provide the test vector to a core scan chain of the core being tested. The bypassed cores are configured such that the associated shift register circuit portion is driven to a hold mode in which storage elements of the shift register circuit portion have their outputs coupled to their inputs. This method provides holding of the shift register stages when a core is bypassed and in a test mode, and this means the shift register stages are less prone to errors resulting from changes in clock signals applied to the shift register stages.

Abstract: A shift register circuit is provided for storing instruction data for the testing of an integrated circuit core. The shift register circuit comprises a plurality of stages, each stage comprising a serial input (si) and a serial output (so) and a parallel output (wir_output) comprising one terminal of a parallel output of the shift register circuit. A first shift register storage element (32) is for storing a signal received from the serial input (si) and providing it to the serial output (so) in a scan chain mode of operation. A second parallel register storage element (38) is for storing a signal from the first shift register storage element (32) and providing it to the parallel output (wir_output) in an update mode of operation. The stage further comprises a feedback path (40) for providing an inverted version of the parallel output (wir_output) to the first shift register storage element (32) in a test mode of operation.