Abstract: A modulated digital input signal is passed through a conditioning circuit to generate a first input signal. An error amplifier circuit receives the first input signal and a second input signal, and controls the operation of a MOS transistor to generate an output signal that is current modulated. The output signal is sensed to generate a feedback signal. A switching circuit selectively applies the feedback signal as the second input signal in response to a transition of the modulated digital input signal from a first logic state to a second logic state. The switching circuit alternatively selectively applies a fixed reference signal as the second input signal to the error amplifier in response to a transition of the modulated digital input signal from the second logic state to the first logic state.

Abstract: A modulated digital input signal is passed through a conditioning circuit to generate a first input signal. An error amplifier circuit receives the first input signal and a second input signal, and controls the operation of a MOS transistor to generate an output signal that is current modulated. The output signal is sensed to generate a feedback signal. A switching circuit selectively applies the feedback signal as the second input signal in response to a transition of the modulated digital input signal from a first logic state to a second logic state. The switching circuit alternatively selectively applies a fixed reference signal as the second input signal to the error amplifier in response to a transition of the modulated digital input signal from the second logic state to the first logic state.

Abstract: A digital input buffer and method. The input buffer includes a voltage regulator configured for operating in weak inversion and outputting a regulated potential, an inverter having as its power source the regulated potential and configured for receiving an input signal, a first latch having its input coupled to the inverter input, and a second latch having its input coupled to the inverter's output, having its output coupled to the first latch's enable input, and having its enable input coupled to the first latch's output. A first latch output signal from the first latch output and a second latch output signal from the second latch output enable switching the first latch output signal to the complement of the input signal and switching the second latch output signal to that of the input signal.

Abstract: An electronic timer may include a clock reference signal generator and a real time clock (RTC) circuit for generating real time data based upon the clock reference signal. The RTC circuit may include a plurality of registers each for storing a respective bit of the real time data. Further, each register may include a master latch for initially storing the real time data bit, a slave latch for subsequently storing the real time data bit, and a user latch for storing the real time data bit from the slave latch. The RTC circuit may further include a controller for causing at least some of the registers to increment based upon the clock reference signal. Additionally, the electronic timer may also advantageously include a tamper circuit for receiving a tamper event signal and causing each of the user latches to hold a time stamp therein.

Abstract: An electronic timer may include a clock reference signal generator and a real time clock (RTC) circuit for generating real time data based upon the clock reference signal. The RTC circuit may include a plurality of registers each for storing a respective bit of the real time data. Further, each register may include a master latch for initially storing the real time data bit, a slave latch for subsequently storing the real time data bit, and a user latch for storing the real time data bit from the slave latch. The RTC circuit may further include a controller for causing at least some of the registers to increment based upon the clock reference signal. Additionally, the electronic timer may also advantageously include a tamper circuit for receiving a tamper event signal and causing each of the user latches to hold a time stamp therein.

Abstract: An electronic timer may include a clock reference signal generator and a real time clock (RTC) circuit for generating real time data based upon the clock reference signal. The RTC circuit may include a plurality of registers each for storing a respective bit of the real time data. Further, each register may include a master latch for initially storing the real time data bit, a slave latch for subsequently storing the real time data bit, and a user latch for storing the real time data bit from the slave latch. The RTC circuit may further include a controller for causing at least some of the registers to increment based upon the clock reference signal. Additionally, the electronic timer may also advantageously include a tamper circuit for receiving a tamper event signal and causing each of the user latches to hold a time stamp therein.

Abstract: A power on reset circuit includes a pulse generation circuit that is connected to receive a supply voltage and respond to an initial ramp-up of that supply voltage to generate an output pulse that transitions from a low to a relatively high state tracking the supply voltage ramp-up. The pulse generation circuit further sets a feedback node in an enable state. Responsive to a flip signal received at an input node, the pulse generation circuit then transitions the output pulse from the relatively high state to the low state and sets the feedback node in a disable state. A static current control transistor switch includes a source-drain circuit coupled to the supply voltage and further includes a gate. The gate is connected to the feedback node such that the transistor switch is actuated in response to the feedback node enable state and unactuated in response to the feedback node disable state.

Abstract: An integrated circuit and method for providing a switchover from the primary power source to the secondary power source to prevent a volatile element from losing stored data. The integrated circuit includes a forced power source switchover circuit for detecting that the supply level of the primary power source drops below a predefined threshold level. A switchover circuit on the integrated circuit initiates a switchover operation based upon the forced power source switchover circuit detecting that the supply level being received from the primary power source drops below the predefined threshold level. The detection by the forced power source switchover circuitry may occur on a signal level that transitions faster than a predetermined negative rate of change. The integrated circuit may be incorporated in any system having volatile elements, such as memory or a clock.

Abstract: A power on reset circuit includes a pulse generation circuit that is connected to receive a supply voltage and respond to an initial ramp-up of that supply voltage to generate an output pulse that transitions from a low to a relatively high state tracking the supply voltage ramp-up. The pulse generation circuit further sets a feedback node in an enable state. Responsive to a flip signal received at an input node, the pulse generation circuit then transitions the output pulse from the relatively high state to the low state and sets the feedback node in a disable state. A static current control transistor switch includes a source-drain circuit coupled to the supply voltage and further includes a gate. The gate is connected to the feedback node such that the transistor switch is actuated in response to the feedback node enable state and unactuated in response to the feedback node disable state.

Abstract: A circuit and method are disclosed for detecting activation of a switch, such as a mechanical switch, having a first terminal coupled to two or more voltage sources, with each voltage source providing a distinct voltage level representing a logic high level. The circuit includes first circuitry, having an output coupled to the switch for initially placing a first voltage across the switch representative of a logic low level. The circuit further includes second circuitry having an input coupled to the switch for sensing a voltage differential appearing across the switch and an output for indicating whether the voltage appearing across the switch is at any voltage representative of the logic high level, the second circuitry being controlled to selectively eliminate static current drawn by the circuit based upon the value of the output of the second circuitry.

Abstract: A circuit and method are disclosed for detecting activation of a switch, such as a mechanical switch. The circuit may include a first circuit for temporarily driving the second terminal of the switch to a second logic level. A second circuit, coupled to the switch, senses a voltage level of the second terminal of the switch and generates an output signal representative of the voltage sensed. A sequential logic circuit is responsive to the output signal of the second circuit so as to maintain a logic value representative of the switch having been closed.

Abstract: A circuit for detecting the state of a switch having a first circuit which substantially periodically attempts to provide a voltage across the switch. A second circuit detects the state of the switch by monitoring the voltage across the switch, and responsively generates an output having a voltage level representative of the voltage appearing across the switch.

Abstract: A circuit for detecting the state of a switch having a first circuit which substantially periodically attempts to provide a voltage across the switch. A second circuit detects the state of the switch by monitoring the voltage across the switch, and responsively generates an output having a voltage level representative of the voltage appearing across the switch.

Abstract: An integrated circuit and method for providing a switchover from the primary power source to the secondary power source to prevent a volatile element from losing stored data. The integrated circuit includes a forced power source switchover circuit for detecting that the supply level of the primary power source drops below a predefined threshold level. A switchover circuit on the integrated circuit initiates a switchover operation based upon the forced power source switchover circuit detecting that the supply level being received from the primary power source drops below the predefined threshold level. The detection by the forced power source switchover circuitry may occur on a signal level that transitions faster than a predetermined negative rate of change. The integrated circuit may be incorporated in any system having volatile elements, such as memory or a clock.

Abstract: An integrated circuit and method for providing a switchover from the primary power source to the secondary power source to prevent a volatile element from losing stored data. The integrated circuit includes a forced power source switchover circuit for detecting that the supply level of the primary power source drops below a predefined threshold level. A switchover circuit on the integrated circuit initiates a switchover operation based upon the forced power source switchover circuit detecting that the supply level being received from the primary power source drops below the predefined threshold level. The detection by the forced power source switchover circuitry may occur on a signal level that transitions faster than a predetermined negative rate of change. The integrated circuit may be incorporated in any system having volatile elements, such as memory or a clock.

Abstract: An electronic timer may include a clock reference signal generator and a real time clock (RTC) circuit for generating real time data based upon the clock reference signal. The RTC circuit may include a plurality of registers each for storing a respective bit of the real time data. Further, each register may include a master latch for initially storing the real time data bit, a slave latch for subsequently storing the real time data bit, and a user latch for storing the real time data bit from the slave latch. The RTC circuit may further include a controller for causing at least some of the registers to increment based upon the clock reference signal. Additionally, the electronic timer may also advantageously include a tamper circuit for receiving a tamper event signal and causing each of the user latches to hold a time stamp therein.

Abstract: A test mode structure and method of a multi-power-source device provides for the device to remain in a test mode, during which current draw of the device may be accurately measured, even after primary power supply to the device has been greatly reduced or completely removed. Significant reduction or removal of the primary power supply while still remaining in the test mode is necessary to counter the presence of a variable current that would otherwise be normally generated by the multi-power-source device in the test mode; the presence of the variable current during the test mode, if not negated, will not permit an accurate measurement of the current draw of the multi-power-source device. Significant reduction or removal of the primary power supply to the device would typically cause the multi-power-source device to exit the test mode and switch to a secondary supply voltage supplied by the secondary power supply, thereby foiling any attempt to measure the current draw of the device.

Abstract: A circuit and method are disclosed for detecting activation of a switch, such as a mechanical switch. The circuit may include a first circuit for temporarily driving the second terminal of the switch to a second logic level. A second circuit, coupled to the switch, senses a voltage level of the second terminal of the switch and generates an output signal representative of the voltage sensed. A sequential logic circuit is responsive to the output signal of the second circuit so as to maintain a logic value representative of the switch having been closed.

Abstract: A circuit and method are disclosed for detecting activation of a switch, such as a mechanical switch, having a first terminal coupled to two or more voltage sources, with each voltage source providing a distinct voltage level representing a logic high level. The circuit includes first circuitry, having an output coupled to the switch for initially placing a first voltage across the switch representative of a logic low level. The circuit further includes second circuitry having an input coupled to the switch for sensing a voltage differential appearing across the switch and an output for indicating whether the voltage appearing across the switch is at any voltage representative of the logic high level, the second circuitry being controlled to selectively eliminate static current drawn by the circuit based upon the value of the output of the second circuitry.

Abstract: A test mode structure and method of a multi-power-source device provides for the device to remain in a test mode, during which current draw of the device may be accurately measured, even after primary power supply to the device has been greatly reduced or completely removed. Significant reduction or removal of the primary power supply while still remaining in the test mode is necessary to counter the presence of a variable current that would otherwise be normally generated by the multi-power-source device in the test mode; the presence of the variable current during the test mode, if not negated, will not permit an accurate measurement of the current draw of the multi-power-source device. Significant reduction or removal of the primary power supply to the device would typically cause the multi-power-source device to exit the test mode and switch to a secondary supply voltage supplied by the secondary power supply, thereby foiling any attempt to measure the current draw of the device.