Abstract: A control apparatus includes multiple processor cores connected to: a monitor that monitors whether a first processor core, the first processor core being any processor core among the multiple processor cores, is operating normally; and a memory having multiple storage areas pre-associated with each of the multiple processor cores. Each of the multiple processor cores periodically writes and updates information to the corresponding storage area in the memory, the information indicating that each of the processor cores is operating normally, and the first processor core determines whether the information in each of the storage areas in the memory has been updated by each of the multiple processor cores, and controls the monitor on the basis of a result of the determination.