Patents by Inventor Tomas Akenine-Moller

Tomas Akenine-Moller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190272440
    Abstract: An image processing method transforms image sequences into luminances, filters the luminances, determines the temporal differences between the luminances, performs a frequency domain transformation on the temporal differences, and applies a temporal contrast sensitivity function envelope integral to the frequency transform output to generate a temporal image metric. The temporal image metric may be applied for example to train a neural network or to configure a display device to depict a visual indication of the temporal image metric.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 5, 2019
    Inventors: Jim Nilsson, Tomas Akenine-Moller
  • Publication number: 20190236166
    Abstract: A method, computer readable medium, and system are disclosed for performing a texture level-of-detail approximation. The method includes the steps of identifying a scene to be rendered, projecting a ray passing through a pixel of a screen space, resulting in a first hit point at a geometry element within the scene, determining a footprint angle of the pixel, determining a curvature measure for the geometry element at the first hit point within the scene, computing a texture level of detail (LOD) approximation for a component of the scene, utilizing the footprint angle of the pixel and the curvature measure for the geometry element, and performing, utilizing a hardware processor, one or more rendering operations for the scene, utilizing the texture LOD approximation.
    Type: Application
    Filed: January 26, 2018
    Publication date: August 1, 2019
    Inventors: Tomas Akenine-Moller, Robert Toth, Magnus Andersson
  • Publication number: 20190236830
    Abstract: A method, computer readable medium, and system are disclosed for performing a texture level-of-detail approximation. The method includes the steps of identifying a scene to be rendered, projecting a ray passing through a pixel of a screen space, resulting in a first hit point at a geometry element within the scene, determining a footprint angle of the pixel, determining a curvature measure for the geometry element at the first hit point within the scene, computing a texture level of detail (LOD) approximation for a component of the scene, utilizing the footprint angle of the pixel and the curvature measure for the geometry element, and performing, utilizing a hardware processor, one or more rendering operations for the scene, utilizing the texture LOD approximation.
    Type: Application
    Filed: June 15, 2018
    Publication date: August 1, 2019
    Inventors: Tomas Akenine-Moller, Robert Toth, Magnus Andersson
  • Publication number: 20190236831
    Abstract: A texture level of detail (LOD) approximation may be performed utilizing ray differentials and a G-buffer. For example, a scene to be rendered is identified, and a G-buffer of the scene is rendered. Additionally, ray tracing is started for the scene, and during the ray tracing, a ray differential is created by accessing the G-buffer. Further, the created ray differential is appended to a current ray, and the created ray differential is traced.
    Type: Application
    Filed: June 28, 2018
    Publication date: August 1, 2019
    Inventors: Tomas Akenine-Moller, Robert Toth, Magnus Andersson, Jim Kjell David Nilsson
  • Publication number: 20190139291
    Abstract: It is presented a method for improving performance of generation of digitally represented graphics. Said method comprises the steps of: selecting (440) a tile comprising fragments to process; executing (452) a culling program for the tile, the culling program being replaceable; and executing a set of instructions, selected from a plurality of sets of instructions based on an output value of the culling program, for each of a plurality of subsets of the fragments. A corresponding display adapter and computer program product are also presented.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Tomas Akenine-Moller, Jon Hasselgren
  • Publication number: 20190139292
    Abstract: It is presented a method for improving performance of generation of digitally represented graphics. Said method comprises the steps of: selecting (440) a tile comprising fragments to process; executing (452) a culling program for the tile, the culling program being replaceable; and executing a set of instructions, selected from a plurality of sets of instructions based on an output value of the culling program, for each of a plurality of subsets of the fragments. A corresponding display adapter and computer program product are also presented.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Tomas Akenine-Moller, Jon Hasselgren
  • Patent number: 9990758
    Abstract: A system rapidly builds bounding volume hierarchies for ray tracing using both the CPU cores and an integrated graphics processor. The hierarchy is built directly into shared memory (between the CPU and GPU). The method starts by sorting the triangles along a space-filling curve, and then quickly sets up a number of mini-trees with a small number of triangles in them, which includes computing the bounding boxes of the mini-trees. This makes it possible to build the mini-trees using a surface-area heuristic in parallel on the graphics processor, while at the same time, the trees above the mini-trees are built in a top-down fashion using the CPU cores.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Per Ganestam, Tomas Akenine-Moller, Carl J. Munkberg
  • Patent number: 9761001
    Abstract: A layered, filtered shadow mapping algorithm may be used for motion blurred shadows. The algorithm is divided into two passes, namely a shadow pass and a lighting pass. The shadow pass renders the scene using stochastic rasterization and generates a time-dependent shadow map augmented with per-sample motion vectors. The subsequent lighting pass renders the scene from the camera's point of view, and performs a shadow query for each sample seen from the camera.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: September 12, 2017
    Assignee: Intel Corporation
    Inventors: Magnus Andersson, Jon N. Hasselgren, Carl J. Munkberg, Tomas Akenine-Moller
  • Patent number: 9665951
    Abstract: A unified compression/decompression architecture is disclosed for reducing memory bandwidth requirements in 3D graphics processing applications. The techniques described erase several distinctions between a texture (compressed once, and decompressed many times), and buffers (compressed and decompressed repeatedly during rendering of an image). An exemplary method for processing graphics data according to one or more embodiments of the invention thus begins with the updating of one or more tiles of a first image array, which are then compressed, using a real-time buffer compression algorithm, to obtain compressed image array tiles. The compressed image array tiles are stored for subsequent use as a texture. During real-time rendering of a second image array, the compressed image array tiles are retrieved and decompressed using a decompression algorithm corresponding to the buffer compression algorithm.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: May 30, 2017
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Jim Rasmusson, Tomas Akenine-Möller, Petrik Clarberg, Jon Hasselgren, Jacob Munkberg
  • Patent number: 9613394
    Abstract: Techniques related to graphics rendering including techniques for color compression and/or decompression using adaptive quantization are described.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: April 4, 2017
    Assignee: INTEL CORPORATION
    Inventors: Tomas Akenine-Moller, Jon Hasselgren, Carl Munkberg, Jim Nilsson, Ariel Berkovits
  • Patent number: 9460552
    Abstract: It is presented a method for improving performance of generation of digitally represented graphics. Said method comprises the steps of: selecting (440) a tile comprising fragments to process; executing (452) a culling program for the tile, the culling program being replaceable; and executing a set of instructions, selected from a plurality of sets of instructions based on an output value of the culling program, for each of a plurality of subsets of the fragments. A corresponding display adapter and computer program product are also presented.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventors: Tomas Akenine-Moller, Jon Hasselgren
  • Publication number: 20160093098
    Abstract: A layered, filtered shadow mapping algorithm may be used for motion blurred shadows. The algorithm is divided into two passes, namely a shadow pass and a lighting pass. The shadow pass renders the scene using stochastic rasterization and generates a time-dependent shadow map augmented with per-sample motion vectors. The subsequent lighting pass renders the scene from the camera's point of view, and performs a shadow query for each sample seen from the camera.
    Type: Application
    Filed: December 18, 2014
    Publication date: March 31, 2016
    Inventors: Magnus Andersson, Jon N. Hasselgren, Carl J. Munkberg, Tomas Akenine-Moller
  • Patent number: 9269180
    Abstract: A computer graphics processor and a method for rendering a three-dimensional image on a display screen. The computer graphics processor comprises a rasterizer configured to perform pixel traversal of a primitive after projection of the primitive. Furthermore, the rasterizer is configured to perform the pixel traversal of a first primitive for a plurality of views prior to performing pixel traversal of a next primitive for one or several views.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Tomas Akenine-Moller, Carl Jacob Munkberg, Jon Hasselgren
  • Publication number: 20150279092
    Abstract: A system rapidly builds bounding volume hierarchies for ray tracing using both the CPU cores and an integrated graphics processor. The hierarchy is built directly into shared memory (between the CPU and GPU). The method starts by sorting the triangles along a space-filling curve, and then quickly sets up a number of mini-trees with a small number of triangles in them, which includes computing the bounding boxes of the mini-trees. This makes it possible to build the mini-trees using a surface-area heuristic in parallel on the graphics processor, while at the same time, the trees above the mini-trees are built in a top-down fashion using the CPU cores.
    Type: Application
    Filed: December 18, 2014
    Publication date: October 1, 2015
    Inventors: Per Ganestam, Tomas Akenine-Moller, Carl J. Munkberg
  • Publication number: 20150062139
    Abstract: Techniques related to graphics rendering including techniques for color compression and/or decompression using adaptive quantization are described.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 5, 2015
    Inventors: Tomas AKENINE-MOLLER, Jon HASSELGREN, Carl MUNKBERG, Jim NILSSON, Ariel BERKOVITS
  • Publication number: 20140320487
    Abstract: A computer graphics processor and a method for rendering a three-dimensional image on a display screen. The computer graphics processor comprises a rasterizer configured to perform pixel traversal of a primitive after projection of the primitive. Furthermore, the rasterizer is configured to perform the pixel traversal of a first primitive for a plurality of views prior to performing pixel traversal of a next primitive for one or several views.
    Type: Application
    Filed: July 9, 2014
    Publication date: October 30, 2014
    Inventors: Tomas Akenine-Moller, Carl Jacob Munkberg, Jon Hasselgren
  • Patent number: 8842121
    Abstract: A single instruction multiple data (SIMD) processor with a given width may operate on registers of the same width completely filled with fragments. A parallel set of registers are loaded and tested. The fragments that fail are eliminated and the register set is refilled from the parallel set.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: September 23, 2014
    Assignee: Intel Corporation
    Inventors: Tomas Akenine-Möller, Jon N. Hasselgren, Carl J. Munkberg, Robert M. Toth, Franz P. Clarberg
  • Patent number: 8824790
    Abstract: A pixel block is compressed by providing a respective color component prediction for each pixel in the block. A difference between color components of two neighboring pixels is calculated and compared to a threshold. If the difference is smaller than the threshold, the prediction is calculated based on a first linear combination of the color components of these two neighboring pixels. However, if the difference exceeds the threshold, a second or third linear combination of the color components of the neighboring pixels is employed in the prediction. A guiding bit associated with the selected linear combination may be used. A prediction error is calculated based on the color component of the pixel and the provided prediction. The compressed block comprises an encoded representation of the prediction error and any guiding bit.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 2, 2014
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Jacob Ström, Per Wennersten, Tomas Akenine-Moller, Jim Rasmusson
  • Patent number: 8803872
    Abstract: A computer graphics processor (20,50) and a method for rendering a three-dimensional image on a display screen. The computer graphics processor (20,50) comprises a rasterizer (23,53) configured to perform pixel traversal of a primitive after projection of the primitive. Furthermore, the rasterizer (23,53) is configured to perform the pixel traversal of a first primitive for a plurality of views prior to performing pixel traversal of a next primitive for one or several views.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: August 12, 2014
    Assignee: Intel Corporation
    Inventors: Tomas Akenine-Möller, Jacob Munkberg, Jon Hasselgren
  • Patent number: 8654122
    Abstract: This relates to a generation of digitally represented graphics. A first representation of a group of vertices is received. A second representation of said group of vertices is determined based on said first representation. A first set of instructions is executed on said second representation of said group of vertices for providing a third representation of said group of vertices, said first set of instructions being associated with vertex position determination. The third representation of said group of vertices is subjected to a culling process.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: February 18, 2014
    Assignee: Intel Corporation
    Inventors: Jon Hasselgren, Jacob Munkberg, Petrik Clarberg, Tomas Akenine-Möller