Abstract: Semiconductor devices, circuits and methods apply both system logic tests and external interface tests via a common series of boundary shift registers residing on the semiconductor chip. In an exemplary embodiment, a test access port receives an external testing signal from a source outside the semiconductor device, and an on-chip test module (e.g. a built-in self-test (BIST) module) contained within the semiconductor device provides an internal testing signal for the system logic. Control logic selectively provides appropriate input testing signals to the boundary shift registers and receives and processes appropriate output signals from the boundary shift registers in each testing mode. Using the various control techniques, a common set of boundary scan registers may be used to implement, for example, an IEEE 1149.1 interface, a BIST isolation wrapper scan chain, a BIST-mode input/output control, or the like.

Abstract: Built-in self test (BIST) capabilities are expanded to provide IDDQ testing of semiconductor chips. Conventional BIST modules generate vectors from a set of pseudo-random pattern generator (PRPG) values. The pseudo-random vectors generated by the set of PRPG values are simulated, and those vectors best suited for an IDDQ test are selected. Each of the IDDQ vectors are identified in a test pattern. During subsequent testing, an IDDQ test of the semiconductor chip can be performed whenever the current test vector applied by the logic BIST corresponds to one of the predetermined IDDQ states.

Abstract: A logic circuit for testing the reliability of an ASIC includes an array circuit having a plurality of matrix arrays each having a plurality of inputs. The plurality of matrix arrays being positioned in a predetermined row and column of the array circuit and being responsive to a plurality of input signals applied thereto for providing a respective row and column output. A parity circuit responsive to the row and column outputs of the plurality of matrix arrays for causing an output signal at an output of the logic circuit to be in a first logic state whenever the row outputs of the plurality of matrix arrays are logically different, or whenever the column outputs of the plurality of matrix arrays are logically different. A stimulus circuit coupled to the plurality of inputs of the plurality of matrix arrays for supplying the plurality of input signals to exhaustively stimulate each one of the plurality of matrix arrays with all possible logic combinations.

Abstract: A design and method of exhaustively verifying the boolean functionality of both combinational and sequential cells for Application Specific Integrted Circuit gate array and standard cell libraries is provided. A single integrated circuit includes a plurality of cells or macros from the library. A Gray code generator provides a plurality of Gray code signals to the cells in response to a binary counter. The binary and Gray code signals stimulate each state of each cell. A multiplexed output indicates the functionality of each state.