Abstract: A system and method for controlling the scheduling of threads in a multi-thread processor system. The multi-thread processor system has a multi-thread processor, a main memory, a cache memory, and a thread scheduler. Information is sent from the cache memory to the thread scheduler for determining which thread the processor is going to execute. The thread scheduler calculates or maintains a figure of merit for each thread executing on the processor. The figure of merit determines which thread to switch to when the current or previous thread has a long latency. The figure of merit define the execution environment as measured by the performance of the cache memory. The figure of merit can be the owner of a particular thread, the number of data lines accessed by a particular thread which resides in the cache, the number of times a particular thread has hit in the cache over a specified time interval, the thread that installed the data or the thread that was used most recently.

Abstract: The method of prefetching data into cache to minimize CPU stall time uses a rough predictor to make rough predictions about what cache lines will be needed next by the CPU. The address difference generator uses the rough prediction and the actual cache miss address to determine the address difference. The prefetch engine builds a data structure to represent address differences and weights them according to the accumulated stall time produced by the cache misses given that the corresponding address is not prefetched.

Abstract: The present invention provides a method and an apparatus for addressing a main memory unit in a computer system which results in improved page hit rate and reduced memory latency by only keeping open some recently used pages and speculatively closing the rest of the pages in the main memory unit. In a computer system with 64 banks and 2 CPUs, only 8 banks may be kept open and the remaining 56 banks are kept closed. Keeping only 8 banks open will not reduce the page hit frequency significantly, but will allow most accesses that are not page hits to access banks that are already closed, so that they are not slowed down by open banks. Thus, the page hit rate is increased and the miss rate is reduced.

Abstract: A main memory indexing scheme optimizes consecutive page hits in computer systems having a main memory system and a cache memory. In accordance with the present invention, one or more bank select bits required by the main memory system are formed from one or more of the address bits that are used by the cache memory as the tag field. Preferably, the lower-order bits of the tag field are used. To increase the page hit rate even further, additional bank select bits are formed from the address bits immediately above the bits used to access columns. In one embodiment of the present invention, address bits are simply mapped to bank bits using a one-to-one correspondence. In another embodiment, address bits from the tag field and address bits immediately above the column bits are combined using a function such as an exclusive-OR operation or an addition operation, with the result of the function provided to the bank select bits.