Patents by Inventor Tomasz Bujewski

Tomasz Bujewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Register sharing mechanism
    Patent number: 10983794
    Abstract: An processor to facilitate register sharing is disclosed. The processor includes a plurality of execution units (EUs), each including a General Purpose Register File (GRF) having a plurality of registers; and register sharing hardware to divide the plurality of registers into a first set of registers dedicated for execution of a first set of threads and a second set of registers shared for execution of a second set of threads.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Guei-Yuan Lueh, Subramaniam Maiyuran, Weiyu Chen, Konrad Trifunovic, Supratim Pal, Chandra S. Gurram, Jorge E. Parra, Pratik J. Ashar, Tomasz Bujewski
  • REGISTER SHARING MECHANISM
    Publication number: 20200394041
    Abstract: An processor to facilitate register sharing is disclosed. The processor includes a plurality of execution units (EUs), each including a General Purpose Register File (GRF) having a plurality of registers; and register sharing hardware to divide the plurality of registers into a first set of registers dedicated for execution of a first set of threads and a second set of registers shared for execution of a second set of threads.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 17, 2020
    Applicant: Intel Corporation
    Inventors: Guei-Yuan Lueh, Subramaniam Maiyuran, Weiyu Chen, Konrad Trifunovic, Supratim Pal, Chandra S. Gurram, Jorge E. Parra, Pratik J. Ashar, Tomasz Bujewski
  • Accumulator pooling mechanism
    Patent number: 10839478
    Abstract: A processor is disclosed. The processor includes an execution unit having a register file having one or more banks of registers to store operand values, an accumulator comprising a pool of registers to store operand values determined to cause a conflict at register banks within the register file and cache circuitry to control storage of the operand values determined to cause a conflict at the register banks from the register file to the pool of registers.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: Guei-Yuan Lueh, Subramaniam Maiyuran, Wei-Yu Chen, Konrad Trifunovic, Supratim Pal, Chandra S. Gurram, Jorge E. Parra, Pratik J. Ashar, Tomasz Bujewski
  • ACCUMULATOR POOLING MECHANISM
    Publication number: 20200320662
    Abstract: A processor is disclosed. The processor includes an execution unit having a register file having one or more banks of registers to store operand values, an accumulator comprising a pool of registers to store operand values determined to cause a conflict at register banks within the register file and cache circuitry to control storage of the operand values determined to cause a conflict at the register banks from the register file to the pool of registers.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 8, 2020
    Applicant: Intel Corporation
    Inventors: Guei-Yuan Lueh, Subramaniam Maiyuran, Wei-Yu Chen, Konrad Trifunovic, Supratim Pal, Chandra S. Gurram, Jorge E. Parra, Pratik J. Ashar, Tomasz Bujewski
  • Vertex shader with primitive replication
    Patent number: 10628910
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine one or more conditions for a set of primitives, and perform primitive replication at a vertex shader based on the determined one or more conditions for the set of primitives. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: April 21, 2020
    Assignee: Intel Corporation
    Inventors: Tomasz Bujewski, Radoslaw Drabinski, Subramaniam Maiyuran, Jorge Garcia Pabon, Raghavendra Miyar, Rajarshi Bajpayee
  • VERTEX SHADER WITH PRIMITIVE REPLICATION
    Publication number: 20200098078
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine one or more conditions for a set of primitives, and perform primitive replication at a vertex shader based on the determined one or more conditions for the set of primitives. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Applicant: Intel Corporation
    Inventors: Tomasz Bujewski, Radoslaw Drabinski, Subramaniam Maiyuran, Jorge Garcia Pabon, Raghavendra Miyar, Rajarshi Bajpayee