Patents by Inventor Tomasz Madajczak

Tomasz Madajczak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230412512
    Abstract: Systems and methods are disclosed for reducing processing for received redundant data streams. A first network controller receives a first stream of data packets and a second network controller receives a second stream of data packets redundant to the first stream. The first network controller determines, using a value of an identifier of a received packet of the first stream of data packets, that a corresponding packet of the second stream of data packets having the value of the identifier has not already been received. In response to the determining, the first network controller outputs the first data packet. The second network controller determines, using a value of an identifier of a second packet of the second stream of data packets, that the first data packet has already been received and drops the second packet in response to the determining.
    Type: Application
    Filed: December 23, 2020
    Publication date: December 21, 2023
    Inventors: Tomasz Madajczak, Pawel Szymanski, Raul Diaz
  • Patent number: 11317098
    Abstract: Apparatus and method for detecting scene changes using data sets gathered from a 3D pipeline. For example, one embodiment of an apparatus comprises: a 3D graphics engine to render a plurality of frames including a current frame and a prior frame; and a scene change detector to retrieve data sets from the 3D graphics engine, the data sets associated with the current frame rendered by the 3D graphics engine, the scene change detector to analyze the data sets in view of corresponding data sets from the prior frame to determine a first type of encoding to be used for encoding the current frame prior to transmission over a network.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: April 26, 2022
    Assignee: INTEL CORPORATION
    Inventors: Tomasz Madajczak, Jaroslaw Motowidlo, James Varga
  • Patent number: 10881956
    Abstract: Techniques related to the render and encode of graphics frames representative of 3D video games are discussed. Such techniques include translating one or more of a transparency map, a depth map, a color compression map, or a motion field used to encode a graphics frame to encode parameters and encoding the first graphics frame using the encode parameters to generate a bitstream.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Tomasz Madajczak, Jason Tanner, Jill Boyce, Changliang Wang, Maciej Oleksy, James Varga, Jr.
  • Publication number: 20200186811
    Abstract: Apparatus and method for detecting scene changes using data sets gathered from a 3D pipeline. For example, one embodiment of an apparatus comprises: a 3D graphics engine to render a plurality of frames including a current frame and a prior frame; and a scene change detector to retrieve data sets from the 3D graphics engine, the data sets associated with the current frame rendered by the 3D graphics engine, the scene change detector to analyze the data sets in view of corresponding data sets from the prior frame to determine a first type of encoding to be used for encoding the current frame prior to transmission over a network.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 11, 2020
    Inventors: TOMASZ MADAJCZAK, JAROSLAW MOTOWIDLO, JAMES VARGA
  • Patent number: 10339624
    Abstract: Systems and methods may provide for receiving a Reverse Polish Notation (RPN) program stream including a set of operands and a set of operations and populating a first register stack with one or more operands in the set of operands. Additionally, one or more registers in the register stack may be powered off based on a stack depth of the register stack. In one example, one or more arguments are read from the register stack and an execution is conducted of one or more operations on the arguments.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventor: Tomasz Madajczak
  • Publication number: 20190141339
    Abstract: Techniques related to the render and encode of graphics frames representative of 3D video games are discussed. Such techniques include translating one or more of a transparency map, a depth map, a color compression map, or a motion field used to encode a graphics frame to encode parameters and encoding the first graphics frame using the encode parameters to generate a bitstream.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Tomasz Madajczak, Jason Tanner, Jill Boyce, Changliang Wang, Maciej Oleksy, James Varga, JR.
  • Publication number: 20170323417
    Abstract: Systems and methods may provide for receiving a Reverse Polish Notation (RPN) program stream including a set of operands and a set of operations and populating a first register stack with one or more operands in the set of operands. Additionally, one or more registers in the register stack may be powered off based on a stack depth of the register stack. In one example, one or more arguments are read from the register stack and an execution is conducted of one or more operations on the arguments.
    Type: Application
    Filed: December 22, 2014
    Publication date: November 9, 2017
    Applicant: Intel Corporation
    Inventor: Tomasz Madajczak
  • Patent number: 8725989
    Abstract: In one embodiment, a processor can perform a function call from a main program to a function that is to operate on at least one vector-type operand, in which only scalar values are passed to the function, and input values to the function including the at least one vector-type operand are to be renamed from virtual registers identified in the function to physical registers of a vector register file, and output values from the function including the at least one vector-type operand are to be renamed from virtual registers identified in the function to physical registers of the vector register file. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: May 13, 2014
    Assignee: Intel Corporation
    Inventor: Tomasz Madajczak
  • Publication number: 20120151182
    Abstract: In one embodiment, a processor can perform a function call from a main program to a function that is to operate on at least one vector-type operand, in which only scalar values are passed to the function, and input values to the function including the at least one vector-type operand are to be renamed from virtual registers identified in the function to physical registers of a vector register file, and output values from the function including the at least one vector-type operand are to be renamed from virtual registers identified in the function to physical registers of the vector register file. Other embodiments are described and claimed.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 14, 2012
    Inventor: Tomasz Madajczak
  • Publication number: 20060004956
    Abstract: According to embodiments of the present invention, a network processor includes a content addressable memory (CAM) unit having CAM arranged in banks and sharable among microengines. In one embodiment, a mask having a value is used to select/enable one group of CAM banks and to deselect/disable another group of CAM banks. A tag may be looked up in the selected/enabled CAM banks based on the mask value. Upon a “miss,” the CAM banks provide the least recently used (LRU) entry. A LRU entry reelection tree may reelect the LRU entry from among all the CAM banks.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventor: Tomasz Madajczak
  • Publication number: 20050188102
    Abstract: A method includes scheduling processing of a packet received by a packet processor with a hardware scheduler in a stack processor included in the packet processor.
    Type: Application
    Filed: December 29, 2003
    Publication date: August 25, 2005
    Inventor: Tomasz Madajczak
  • Publication number: 20050047439
    Abstract: According to some embodiments, a portion of a network packet is received, a sequence number is retrieved, a sequence number is passed to a sequence election unit, a signal to process the packet is received from the sequence election unit, and processing is performed on the packet in response to receipt of the signal.
    Type: Application
    Filed: August 26, 2003
    Publication date: March 3, 2005
    Inventor: Tomasz Madajczak