Abstract: There is provided a system and method of prefetching array segments. A prefetcher management unit (PMU) is disclosed. The PMU includes an interface to interact with programs via an application programming interface (API) and one or more data structures configured to store a plurality of addresses, each of the plurality of addresses representing a memory location of data stored in an array segment. The PMU also includes a prefetcher interface configured to use an address in the one or more data structures to instruct a prefetcher to prefetch data into a cache and a load-store unit interface configured to use the address in the one or more data structures to instruct a load-store unit to load data from the cache.

Abstract: There is provided methods and devices for dynamically simplifying processor instructions. A method includes receiving, at a computing device, processor instructions and determining, by the computing device, if instruction simplification is enabled for an instruction being processed. The method further includes determining, by the computing device, from an instruction simplification table if the instruction is capable of being simplified and scheduling, by the computing device, a simplified instruction based on the determination from the instruction simplification table. A device includes a processor, and a non-transient computer readable memory having stored thereon instructions which when executed by the processor configure the device to execute the methods disclosed herein.

Abstract: There is provided methods and devices for dynamically simplifying processor instructions. A method includes receiving, at a computing device, processor instructions and determining, by the computing device, if instruction simplification is enabled for an instruction being processed. The method further includes determining, by the computing device, from an instruction simplification table if the instruction is capable of being simplified and scheduling, by the computing device, a simplified instruction based on the determination from the instruction simplification table. A device includes a processor, and a non-transient computer readable memory having stored thereon instructions which when executed by the processor configure the device to execute the methods disclosed herein.

Abstract: Systems and methods for calculating a dot product using digital signal processing units that are organized into a dot product processing unit for dot product processing using multipliers and adders of the digital signal processing units.

Abstract: Systems and methods for calculating a dot product using digital signal processing units that are organized into a dot product processing unit for dot product processing using multipliers and adders of the digital signal processing units.

Abstract: Systems and methods for using single-precision floating-point operation digital signal processing (DSP) blocks in conjunction to perform double-precision floating-point operations.

Abstract: Systems and methods for calculating a dot product using digital signal processing units that are organized into a dot product processing unit for dot product processing using multipliers and adders of the digital signal processing units.

Abstract: An integrated circuit is provided that performs floating-point operations involving at least two successive computational steps. Two floating-point numbers entering any additional computational step after the first computational step are aligned dynamically by shifting the mantissa of the floating-point number with the greater exponent to the left and the mantissa of the floating-point number with the smaller exponent to the right. The number of left shift bits is dependent on the magnitude of the difference between the two floating-point exponents and the number of leading zeroes in the mantissa with the greater exponent. The number of right shift bits is dependent on the magnitude of the difference between the two floating-point exponents and the number of left shift bits.