Patents by Inventor TOMASZ SZUPRYCINSKI

TOMASZ SZUPRYCINSKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11222707
    Abstract: A system-on-chip (SoC) includes a fuse circuit and decoding circuitry. The fuse circuit includes functional fuses, control fuses utilized as the functional fuses, and fuses configured to store override data that indicates an association between the functional fuses and the control fuses utilized as the functional fuses. The decoding circuitry is configured to output configuration data associated with a configuration of the fuse circuit based on the override data and an initial configuration of the fuse circuit. In such a scenario, functional operations of the SoC are executed based on the configuration data. Alternatively, the decoding circuitry is configured to output a set of functional data based on the override data and various functional data stored in the functional fuses and the control fuses utilized as the functional fuses. In such a scenario, the functional operations are executed based on the outputted set of functional data.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: January 11, 2022
    Assignee: NXP USA, Inc.
    Inventors: Rohit Kumar Sinha, Tomasz Szuprycinski, Deepak Mahajan, Ruchi Bora
  • Patent number: 11057396
    Abstract: An intelligent transportation system, ITS, station (600) comprising: a host processor (640); and a memory (664) operably coupled to the host processor (640). The host processor (640) is configured to: perform verification per identity that includes precomputation of data for a plurality of neighbouring ITS stations of the ITS station (600); store precomputation data for the verified identity of the plurality of neighbouring ITS stations in the memory (664); and extract from memory (664) and use the stored precomputation data for a respective neighbouring ITS station to perform an accelerated verification of a subsequent message received from that neighbouring ITS station.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: July 6, 2021
    Assignee: NXP B.V.
    Inventors: Artur Burchard, Tomasz Szuprycinski
  • Patent number: 11049395
    Abstract: An intelligent transportation system, ITS, station (600) comprising: a host processor (640); and a memory (664) operably coupled to the host processor (640). The host processor (640) is configured to: perform precomputation of certificate data associated with an identity to be verified on a per identity basis; store precomputation data for a plurality of verified identities in the memory (664); and extract stored precomputation data from memory (664) and use the stored precomputation data to perform accelerated verification of subordinate certificates.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: June 29, 2021
    Assignee: NXP B.V.
    Inventors: Tomasz Szuprycinski, Artur Tadeusz Burchard
  • Publication number: 20180288069
    Abstract: An intelligent transportation system, ITS, station (600) comprising: a host processor (640); and a memory (664) operably coupled to the host processor (640). The host processor (640) is configured to: perform verification per identity that includes precomputation of data for a plurality of neighbouring ITS stations of the ITS station (600); store precomputation data for the verified identity of the plurality of neighbouring ITS stations in the memory (664); and extract from memory (664) and use the stored precomputation data for a respective neighbouring ITS station to perform an accelerated verification of a subsequent message received from that neighbouring ITS station.
    Type: Application
    Filed: February 27, 2018
    Publication date: October 4, 2018
    Inventors: Artur Burchard, Tomasz Szuprycinski
  • Publication number: 20180286229
    Abstract: An intelligent transportation system, ITS, station (600) comprising: a host processor (640); and a memory (664) operably coupled to the host processor (640). The host processor (640) is configured to: perform precomputation of certificate data associated with an identity to be verified on a per identity basis; store precomputation data for a plurality of verified identities in the memory (664); and extract stored precomputation data from memory (664) and use the stored precomputation data to perform accelerated verification of subordinate certificates.
    Type: Application
    Filed: March 6, 2018
    Publication date: October 4, 2018
    Inventors: TOMASZ SZUPRYCINSKI, Artur Tadeusz Burchard