Patents by Inventor Tomer Bar-On

Tomer Bar-On has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220005259
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 22, 2021
    Publication date: January 6, 2022
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer KP, Jonathan Kennedy, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Tomer Bar-On, Carsten Benthin, Adam T. Lake, Vasanth Ranganathan, Abhishek R. Appu
  • Patent number: 11216915
    Abstract: Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: January 4, 2022
    Assignee: Intel Corporation
    Inventors: Tomer Bar-On, Hugues Labbe, Adam T. Lake, Kai Xiao, Ankur N. Shah, Johannes Guenther, Abhishek R. Appu, Joydeep Ray, Deepak S. Vembar, ElMoustapha Ould-Ahmed-Vall
  • Patent number: 11210265
    Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: December 28, 2021
    Assignee: INTEL CORPORATION
    Inventors: Altug Koker, Prasoonkumar Surti, David Puffer, Subramaniam Maiyuran, Guei-Yuan Lueh, Abhishek R. Appu, Joydeep Ray, Balaji Vembu, Tomer Bar-On, Andrew T. Lauritzen, Hugues Labbe, John G. Gierach, Gabor Liktor
  • Patent number: 11182948
    Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 23, 2021
    Assignee: Intel Corporation
    Inventors: Hugues Labbe, Tomer Bar-On, Gabor Liktor, Andrew T. Lauritzen, John G. Gierach
  • Patent number: 11182296
    Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: November 23, 2021
    Assignee: Intel Corporation
    Inventors: Andrew T. Lauritzen, Gabor Liktor, Tomer Bar-On, Hugues Labbe, John G. Gierach, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, Balaji Vembu, Altug Koker
  • Publication number: 20210350585
    Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 10, 2021
    Publication date: November 11, 2021
    Applicant: INTEL CORPORATION
    Inventors: Tomer Bar-On, Jacob Subag, Yaniv Fais, Jeremie Dreyfuss, Gal Novik, Gal Leibovich, Tomer Schwartz, Ehud Cohen, Lev Faivishevsky, Uzi Sarel, Amitai Armon, Yahav Shadmiy
  • Patent number: 11132601
    Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: September 28, 2021
    Assignee: INTEL CORPORATION
    Inventors: Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Jeremie Dreyfuss, Amit Bleiweiss, Tomer Schwartz
  • Patent number: 11107444
    Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Travis Schluessler, Abhishek Venkatesh, John Gierach, Tomer Bar-On, Devan Burke
  • Patent number: 11100393
    Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: August 24, 2021
    Assignee: INTEL CORPORATION
    Inventors: Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Jeremie Dreyfuss, Amit Bleiweiss, Tomer Schwartz
  • Publication number: 20210256272
    Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to save one or more outputs of a deep learning neural network in a storage system of an autonomous vehicle and upload the one or more outputs to a remote server. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: February 12, 2021
    Publication date: August 19, 2021
    Applicant: Intel Corporation
    Inventors: Jeremie Dreyfuss, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Eran Ben-Avi, Neta Zmora, Tomer Schwartz
  • Patent number: 11093822
    Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: August 17, 2021
    Assignee: INTEL CORPORATION
    Inventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Amit Bleiweiss, Gal Leibovich, Jeremie Dreyfuss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag
  • Patent number: 11082467
    Abstract: The present disclosure relates to systems, non-transitory computer-readable media, and methods for accurately, flexibly, and efficiently broadcasting public combined live video streams from multiple participant devices, which change over the course of the live broadcast, as well as generating dynamic user interfaces that streamline adding, removing, and swapping participant devices from the public combined live video stream. In particular, a live video streaming system facilitates compositing live video streams from multiple participant devices into a public combined live video stream within a digital room before broadcasting the public combined live video stream to viewer devices.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: August 3, 2021
    Assignee: FACEBOOK, INC.
    Inventors: Allison Hartnett, Kristin Lindsey George, Abhishek Parthasarathy, Hemal Khatri, Tomer Bar
  • Patent number: 11037330
    Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 8, 2017
    Date of Patent: June 15, 2021
    Assignee: INTEL CORPORATION
    Inventors: Tomer Bar-On, Jacob Subag, Yaniv Fais, Jeremie Dreyfuss, Gal Novik, Gal Leibovich, Tomer Schwartz, Ehud Cohen, Lev Faivishevsky, Uzi Sarel, Amitai Armon, Yahav Shadmiy
  • Patent number: 11017494
    Abstract: An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Hugues Labbe, Tomer Bar-On, Kai Xiao, Ankur N. Shah, John G. Gierach
  • Publication number: 20210150798
    Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.
    Type: Application
    Filed: December 18, 2020
    Publication date: May 20, 2021
    Applicant: Intel Corporation
    Inventors: Hugues Labbe, Tomer Bar-On, Gabor Liktor, Andrew T. Lauritzen, John G. Gierach
  • Publication number: 20210141604
    Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 13, 2021
    Applicant: Intel Corporation
    Inventors: Yaniv Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby
  • Patent number: 10977847
    Abstract: A video effects application executes on a client device having an image capture device and receives video data captured by the image capture device. The video effects application extracts information from the captured video data and stores the extracted information as metadata associated with the captured video data. For example, the video effects application identifies objects in the captured video data or identifies optical flow of the captured video data and stores the identified objects or identified optical flow as metadata associated with the captured video data. The video effects application stores information describing modifications to the captured video data in association with the captured video data. When the captured video data is presented, the captured video data, associated metadata, and information describing the modifications is communicated to a renderer, which uses the metadata to perform the identified modifications to the captured video data when presenting the captured video data.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: April 13, 2021
    Assignee: Facebook, Inc.
    Inventors: Hermes Germi Pique Corchs, Kirill A. Pugin, Razvan Gabriel Racasanu, Colin Todd Miller, Ragavan Srinivasan, Tomer Bar, Bryce David Redd
  • Patent number: 10957096
    Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 23, 2021
    Assignee: hiel Corporation
    Inventors: Hugues Labbe, Tomer Bar-On, Gabor Liktor, Andrew T. Lauritzen, John G. Gierach
  • Patent number: 10957050
    Abstract: Systems, apparatuses and methods may provide for technology that partitions a three-dimensional (3D) scene into a plurality of layers including at least a foreground layer and a background layer. Additionally, the foreground layer may be rendered at a first rate and the background layer may be rendered at a second frame rate, wherein the first frame rate is greater than the second frame rate. In one example, the foreground layer and the background layer are composited into a frame.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Hugues Labbe, Tomer Bar-On, John G. Gierach, Gabor Liktor, Andrew T. Lauritzen
  • Patent number: 10937126
    Abstract: Embodiments are generally directed to tile-based multiple resolution rendering of images. An embodiment of an apparatus includes one or more processor cores; a plurality of tiling bins, the plurality of tiling bins including a bin for each of a plurality of tiles in an image; and a memory to store data for rendering of an image in one or more of a plurality of resolutions. The apparatus is to generate, in the memory, storage for a resolution setting for each the plurality of tiling bins and storage for a final render target, each tile of the final render target being rendered based on a respective tiling bin in the plurality of tiling bins.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: March 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: John Gierach, Abhishek Venkatesh, Travis Schluessler, Devan Burke, Tomer Bar-On, Michael Apodaca