Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to store data according to a second memory storage process instead of a first memory storage process based on an underfill threshold.

Abstract: For bit errors caused by intrinsic cell variations, the bit errors are scattered across a page of memory. However, for bit errors caused by a physical issue in memory, the bit errors cluster together within the same memory area. In an example data storage device, a page of memory is divided into sections, and counters are used to count the number of errors in each section. A physical error location is detected if the number exceeds a parameter, and as compared to the number of errors in the other sections. In another example data storage device having an error correction code (ECC) engine, a histogram and binomial probability are used to detect physical errors. This has the advantage of detecting weak memory blocks that are about to fail, so the blocks can be retired early as a grown bad block.

Abstract: Aspects of the present disclosure configure a memory sub-system controller to read data from a first portion of a memory based on read levels previously established while reading a second portion of the memory. The controller receives a request to read data from a first portion of a set of memory components. The controller identifies a second portion of the set of memory components that has been programmed with data within a threshold period of time of programming the data in the first portion. The controller retrieves a set of read threshold levels that have been previously computed in association with reading the data from the second portion. The controller reads the data from the first portion using the set of read threshold levels that have been previously computed in association with reading the data from the second portion.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide superblock management based on memory component reliabilities.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide superbkock management based on memory component reliabilities.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide superblock management based on memory component reliabilities.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to store data according to a second memory storage process instead of a first memory storage process based on an underfill threshold.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine a read threshold on a wordline, adjust a read threshold voltage level associated with the read threshold, determine an adjusted read threshold at the adjusted read threshold voltage level, where the adjusted read threshold is different from the read threshold, compare the adjusted read threshold to the read threshold, and calibrate the read threshold based on the comparing. The controller is further configured to analyze a bit error rate (BER) difference based on the calibrating and/or a previous read threshold voltage level movement, choose a next target read threshold for next calibration, and read a second page at the next target read threshold.

Abstract: Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the source line. When a program operation involves the drain-side sub-block, the NAND strings are pre-charged from the bit line. When a program operation involves an interior sub-block, the NAND strings can be pre-charged from the bit line if all sub-blocks on the drain side of the interior sub-block are erased, or from the source line if all sub-blocks on the source side of the interior sub-block are erased. A table can be provided which identifies free blocks, free sub-blocks and a corresponding program order. If such a table is not available, the sub-blocks can be read to determine whether they are programmed.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine a read threshold on a wordline, adjust a read threshold voltage level associated with the read threshold, determine an adjusted read threshold at the adjusted read threshold voltage level, where the adjusted read threshold is different from the read threshold, compare the adjusted read threshold to the read threshold, and calibrate the read threshold based on the comparing. The controller is further configured to analyze a bit error rate (BER) difference based on the calibrating and/or a previous read threshold voltage level movement, choose a next target read threshold for next calibration, and read a second page at the next target read threshold.

Abstract: Technology is disclosed for an efficient read NAND memory cells while mitigating read disturb. In an aspect, a read sequence includes a read spike that removes residual electrons from the NAND channels, followed by reading multiple different groups of memory cells, followed by a channel clean operation. The read spike and channel clean mitigate read disturb. The read spike and channel clean each take a significant amount of time to perform. However, since multiple groups of memory cells are read between the read spike and channel clean this time is essentially spread over the reading of multiple groups, thereby improving the average time to read a single group of memory cells. In one aspect, reading the multiple different groups of memory cells includes reading one or more pages from each of the groups of memory cells. In one aspect, each group is in a different sub-block.

Abstract: Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the source line. When a program operation involves the drain-side sub-block, the NAND strings are pre-charged from the bit line. When a program operation involves an interior sub-block, the NAND strings can be pre-charged from the bit line if all sub-blocks on the drain side of the interior sub-block are erased, or from the source line if all sub-blocks on the source side of the interior sub-block are erased. A table can be provided which identifies free blocks, free sub-blocks and a corresponding program order. If such a table is not available, the sub-blocks can be read to determine whether they are programmed.

Abstract: Technology is disclosed for an efficient read NAND memory cells while mitigating read disturb. In an aspect, a read sequence includes a read spike that removes residual electrons from the NAND channels, followed by reading multiple different groups of memory cells, followed by a channel clean operation. The read spike and channel clean mitigate read disturb. The read spike and channel clean each take a significant amount of time to perform. However, since multiple groups of memory cells are read between the read spike and channel clean this time is essentially spread over the reading of multiple groups, thereby improving the average time to read a single group of memory cells. In one aspect, reading the multiple different groups of memory cells includes reading one or more pages from each of the groups of memory cells. In one aspect, each group is in a different sub-block.

Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die based on one or more operational parameters. The control die is configured to calibrate the one or more operational parameters for the memory die. The control die is also configured to perform testing of the memory die using the calibrated one or more operational parameters.

Abstract: A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled to the first memory cell, and a third bitline voltage is applied to the bitline coupled to the second memory cell. The second bitline voltage is greater than the first bitline voltage to reduce a programming speed of the first bitline voltage to increase a programming speed of the second memory cell.

Abstract: In the context of data storage, an approach to pre-fetching data prior to a read request involves receiving a read request and a next read request, and updating metadata corresponding to the read request with a next data storage address corresponding to the next read request. Responsive to again receiving the read request at a later time, the next data storage address can be read from the read request metadata and the next data can be pre-fetched from the next data storage address in advance of processing a following read request. Furthermore, the next data can be pre-fetched during read queue idle time and stored in a cache buffer, in anticipation of another incoming next read request, responsive to which the next data can be returned to the host from the buffer rather than from a read of non-volatile memory.

Abstract: A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled to the first memory cell, and a third bitline voltage is applied to the bitline coupled to the second memory cell. The second bitline voltage is greater than the first bitline voltage to reduce a programming speed of the first bitline voltage to increase a programming speed of the second memory cell.

Abstract: A storage device includes a controller that can dynamically adjust the zone active limit (ZAL) for a zoned namespace (ZNS). Rather than assuming a worst-case scenario for the ZNS, the ZAL can be dynamically adjusted, even after providing the ZAL to a host device. In so doing, device behavior changes due to factors such as temperature, failed or flipped bit count, and device cycling can be considered as impacting the ZAL. The ZAL can then be adjusted over time, and the new ZAL can be communicated to the host device. As such, rather than a fixed, worst-case ZAL, the host device will receive updated ZAL values over time as the device performs.

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in a plurality of planes. The apparatus also includes a control circuit coupled to the word lines and the bit lines and configured to determine whether a program operation of the memory cells involves all of the plurality of planes. In response to the program operation of the memory cells not involving all of the plurality of planes, the control circuit adjusts at least one of a bit line ramp rate of a bit line voltage applied to the bit lines and a word line ramp rate of at least one word line voltage applied to the word lines during the program operation based on a quantity of the plurality of planes associated with the memory cells being program-verified in the program operation.

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in a plurality of planes. The apparatus also includes a control circuit coupled to the word lines and the bit lines and configured to determine whether a program operation of the memory cells involves all of the plurality of planes. In response to the program operation of the memory cells not involving all of the plurality of planes, the control circuit adjusts at least one of a bit line ramp rate of a bit line voltage applied to the bit lines and a word line ramp rate of at least one word line voltage applied to the word lines during the program operation based on a quantity of the plurality of planes associated with the memory cells being program-verified in the program operation.