Patents by Inventor TOMER STARK
TOMER STARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230273846Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.Type: ApplicationFiled: May 8, 2023Publication date: August 31, 2023Inventors: Tomer Stark, Ron Gabor, Joseph Nuzman, Raanan Sade, Bryant E. Bigbee
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Patent number: 11693785Abstract: An apparatus and method for tagged memory management.Type: GrantFiled: December 27, 2019Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Ron Gabor, Enrico Perla, Raanan Sade, Igor Yanover, Tomer Stark, Joseph Nuzman
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Patent number: 11656998Abstract: An apparatus and method for tagged memory management, an embodiment including execution circuitry to generate a system memory access request having a first address pointer and address translation circuitry to determine whether to translate the first address pointer with metadata processing. The address translation circuitry is to access address translation tables to translate the first address pointer to a first physical address, perform a lookup in a memory metadata table to identify a memory metadata value associated with a physical address range including the first physical address, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value; and when the comparison results in a validation of the memory access request, then return the first physical address.Type: GrantFiled: December 28, 2019Date of Patent: May 23, 2023Assignee: Intel CorporationInventors: Ron Gabor, Enrico Perla, Raanan Sade, Igor Yanover, Tomer Stark
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Patent number: 11645135Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.Type: GrantFiled: September 14, 2020Date of Patent: May 9, 2023Assignee: Intel CorporationInventors: Tomer Stark, Ron Gabor, Joseph Nuzman, Raanan Sade, Bryant E. Bigbee
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Patent number: 11392503Abstract: An apparatus and method for tagged memory management.Type: GrantFiled: December 27, 2019Date of Patent: July 19, 2022Assignee: INTEL CORPORATIONInventors: Ron Gabor, Raanan Sade, Igor Yanover, Assaf Zaltsman, Tomer Stark
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Publication number: 20210200686Abstract: An apparatus and method for tagged memory management.Type: ApplicationFiled: December 27, 2019Publication date: July 1, 2021Inventors: RON GABOR, RAANAN SADE, IGOR YANOVER, ASSAF ZALTSMAN, TOMER STARK
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Publication number: 20210200684Abstract: An apparatus and method for tagged memory management.Type: ApplicationFiled: December 27, 2019Publication date: July 1, 2021Inventors: RON GABOR, ENRICO PERLA, RAANAN SADE, IGOR YANOVER, TOMER STARK, JOSEPH NUZMAN
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Patent number: 11030030Abstract: One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.Type: GrantFiled: January 28, 2019Date of Patent: June 8, 2021Assignee: Intel CorporationInventors: Tomer Stark, Ron Gabor, Joseph Nuzman
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Publication number: 20210141683Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.Type: ApplicationFiled: September 14, 2020Publication date: May 13, 2021Inventors: Tomer Stark, Ron Gabor, Joseph Nuzman, Raanan Sade, Bryant E. Bigbee
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Patent number: 10976961Abstract: Techniques and mechanisms for circuitry of a processor to automatically provide, and perform an operation based on, metadata indicating an uninitialized memory block. In an embodiment, processor circuitry detects a software instruction which specifies a first operation to be performed based on some data at a memory block. Metadata corresponding to said data comprises an identifier of whether the data is based on an uninitialized memory condition. Processing of the instruction, includes the processor circuitry automatically performing a second operation based on the identifier. The second operation is performed independent of any instruction of the application which specifies the second operation. In another embodiment, execution of the instruction (if any) is conditional upon an evaluation which is based on the state identifier, or the second operation is automatically performed based on an execution of the first instruction.Type: GrantFiled: December 20, 2018Date of Patent: April 13, 2021Assignee: Intel CorporationInventors: Ron Gabor, Tomer Stark, Joseph Nuzman, Ady Tal
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Patent number: 10776190Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.Type: GrantFiled: December 18, 2018Date of Patent: September 15, 2020Assignee: Intel CorporationInventors: Tomer Stark, Ron Gabor, Joseph Nuzman, Raanan Sade, Bryant E. Bigbee
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Publication number: 20200201567Abstract: Techniques and mechanisms for circuitry of a processor to automatically provide, and perform an operation based on, metadata indicating an uninitialized memory block. In an embodiment, processor circuitry detects a software instruction which specifies a first operation to be performed based on some data at a memory block. Metadata corresponding to said data comprises an identifier of whether the data is based on an uninitialized memory condition. Processing of the instruction, includes the processor circuitry automatically performing a second operation based on the identifier. The second operation is performed independent of any instruction of the application which specifies the second operation. In another embodiment, execution of the instruction (if any) is conditional upon an evaluation which is based on the state identifier, or the second operation is automatically performed based on an execution of the first instruction.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Applicant: Intel CorporationInventors: Ron Gabor, Tomer Stark, Joseph Nuzman, Ady Tal
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Patent number: 10585741Abstract: Memory corruption detection technologies are described. A processor core of a processor can receive a first pointer produced by a first memory access instruction of an application being executed by the processor. The first pointer includes a first memory address of a first memory object and a third metadata value and the memory address identifies a memory block in the first set of one or more contiguous memory blocks. The processor core compares the third metadata value to the first metadata value and communicates a memory corruption detection message to the application when the third metadata value does not match the first metadata value. The processor core provides the first memory object to the application when the third metadata value matches the first metadata value.Type: GrantFiled: September 6, 2018Date of Patent: March 10, 2020Assignee: Intel CorporationInventors: Tomer Stark, Ady Tal, Ron Gabor
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Patent number: 10521361Abstract: Memory corruption detection technologies are described. A method may store in a register an address of a memory corruption detection (MCD) table. The method receives, from an application, a memory store request to store data in a first portion of a contiguous memory block of a memory and sends, to the application, a fault message when a fault event associated with the first portion occurs in view of a protection mode of the first portion, wherein the protection mode indicates that the first portion is write protected.Type: GrantFiled: February 26, 2018Date of Patent: December 31, 2019Assignee: Intel CorporationInventors: Tomer Stark, Ron Gabor, Ady Tal, Joseph Nuzman
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Publication number: 20190235948Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.Type: ApplicationFiled: December 18, 2018Publication date: August 1, 2019Inventors: Tomer Stark, Ron Gabor, Joseph Nuzman, Raanan Sade, Bryant E. Bigbee
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Publication number: 20190235938Abstract: One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.Type: ApplicationFiled: January 28, 2019Publication date: August 1, 2019Applicant: Intel CorporationInventors: TOMER STARK, RON GABOR, JOSEPH NUZMAN
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Patent number: 10191791Abstract: One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.Type: GrantFiled: July 2, 2016Date of Patent: January 29, 2019Assignee: Intel CorporationInventors: Tomer Stark, Ron Gabor, Joseph Nuzman
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Publication number: 20190004886Abstract: Memory corruption detection technologies are described. A processor core of a processor can receive a first pointer produced by a first memory access instruction of an application being executed by the processor. The first pointer includes a first memory address of a first memory object and a third metadata value and the memory address identifies a memory block in the first set of one or more contiguous memory blocks. The processor core compares the third metadata value to the first metadata value and communicates a memory corruption detection message to the application when the third metadata value does not match the first metadata value. The processor core provides the first memory object to the application when the third metadata value matches the first metadata value.Type: ApplicationFiled: September 6, 2018Publication date: January 3, 2019Inventors: Tomer Stark, Ady Tal, Ron Gabor
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Patent number: 10162694Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.Type: GrantFiled: December 21, 2015Date of Patent: December 25, 2018Assignee: Intel CorporationInventors: Tomer Stark, Ron Gabor, Joseph Nuzman, Raanan Sade, Bryant E. Bigbee
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Patent number: 10095573Abstract: Memory corruption detection technologies are described. A processor can include a memory to store a memory corruption detection (MCD) table. A processor core of the processor can receive, from an application, an allocation request for an allocation of a memory object within a contiguous memory block in the memory. The processor core can allocate the contiguous memory block in view of a size of the memory object requested and write MCD meta-data into the MCD table, including a MCD identifier (ID) associated with the contiguous memory block and a MCD border value indicating a size of a memory region of the contiguous memory block.Type: GrantFiled: September 18, 2017Date of Patent: October 9, 2018Assignee: Intel CorporationInventors: Tomer Stark, Ady Tal, Ron Gabor, Joseph Nuzman