Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: Implementations described herein relate to detecting a memory write reliability risk without using a write verify operation. In some implementations, a memory device may perform a program operation that includes a single program pulse and that does not include a program verify operation immediately after the single program pulse. The memory device may set a flag value based on comparing a transition time and a transition time threshold. The transition time may be a time to transition from a first voltage to a second voltage during the program operation. The memory device may selectively perform a mitigation operation based on whether the flag value is set to a first value or a second value.

Abstract: Methods, systems, and devices for error detection for programming single level cells of a memory system are described. The memory system may receive a write command for writing data to a block of memory cells and generate a write voltage to write the data to the block of memory cells. The memory system may compare the write voltage to a reference voltage and determine whether the write voltage satisfies a threshold tolerance associated with the reference voltage. The memory system may generate signaling indicating an error associated with writing the data to the block of memory cells, based on determining that the write voltage does not satisfy the threshold tolerance.

Abstract: Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

Abstract: Disclosed are systems and methods for efficient power management for storage devices. A method includes receiving a request to transition a flash memory to a first stand-by mode, wherein the flash memory comprises a plurality of dies. The method also includes causing one or more guard dies of the plurality of dies to transition to the first stand-by mode while causing one or more other dies of the plurality of dies to transition to a second stand-by mode, wherein the second stand-by mode is configured to consume less power than the first stand-by mode. The method also includes receiving an input/output (I/O) request for the flash memory. The method also includes causing the I/O request to be performed on the one or more guard dies that are in the first stand-by mode but not in the second stand-by mode.

Abstract: Systems and methods for storing data are described. A system can comprise a controller, one or more physical non-volatile memory devices, a bus comprising a plurality of input/output (I/O) lines. The controller configured to receive data, encode the received data into a codeword, and transfer, in parallel, different portions of the codeword to different physical non-volatile memory devices among the plurality of physical non-volatile memory devices.

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: Apparatus, media, methods, and systems for data storage systems and methods for optimized scheduling of background management operations. A data storage system may comprise a controller. The controller is configured to determine a timeout value of an adaptive timeout parameter of the data storage system. The controller is configured to determine whether a first host operation is received. The controller is configured to, when the first host operation is not received, determine whether the timeout value satisfies a threshold value. The controller is configured to, when the timeout value satisfies the threshold value, cause one or more background management operations to be executed at the data storage system.

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: Methods and apparatus for use with non-volatile memory (NVM) arrays having single-level cell (SLC) layers and multi-level cell (MLC) layers, such as triple-level cell (TLC) layers, provide for a coupled SLC/MLC write operation where SLC write protection is combined into a MLC write flow. In an illustrative example, data is written concurrently to SLC and TLC. The SLC data provides a backup for the TLC data in the event the TLC data is defective. The TLC data is verified using, for example, write verification. If the data is successfully verified, the SLC block can be erased or otherwise overwritten with new data. If not, the SLC block can be used to recover the data for storage in a different TLC block. The coupled SLC/MLC write operation may be performed in conjunction with a quick pass write (QPW).

Abstract: Systems and methods for storing data are described. A system can comprise a controller, one or more physical non-volatile memory devices, a bus comprising a plurality of input/output (I/O) lines. The controller configured to receive data, encode the received data into a codeword, and transfer, in parallel, different portions of the codeword to different physical non-volatile memory devices among the plurality of physical non-volatile memory devices.

Abstract: A method, device, and system for improving read performance in frequently changing device temperature conditions through detecting thermal region tags and thermal region outliers in a memory device. A plurality of thermal regions may be configured for the memory device. A first temperature may be measured corresponding to opening a storage block of the memory device for programming. A second temperature may then be measured corresponding to closing the storage block for programming. A range between the first temperature and the second temperature may be determined. The range may span N?2 of the thermal regions. Finally, the storage block may be assigned to a thermal region that includes the second temperature, on condition that N satisfies a threshold.

Abstract: A method, device, and system for improving read performance in frequently changing device temperature conditions through detecting thermal region tags and thermal region outliers in a memory device. A plurality of thermal regions may be configured for the memory device. A first temperature may be measured corresponding to opening a storage block of the memory device for programming. A second temperature may then be measured corresponding to closing the storage block for programming. A range between the first temperature and the second temperature may be determined. The range may span N?2 of the thermal regions. Finally, the storage block may be assigned to a thermal region that includes the second temperature, on condition that N satisfies a threshold.

Abstract: Systems and methods for storing data are described. A system can comprise a controller, one or more physical non-volatile memory devices, a bus comprising a plurality of input/output (I/O) lines. The controller configured to receive data, encode the received data into a codeword, and transfer, in parallel, different portions of the codeword to different physical non-volatile memory devices among the plurality of physical non-volatile memory devices.

Abstract: Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

Abstract: Methods and apparatus for use with non-volatile memory (NVM) arrays having single-level cell (SLC) layers and multi-level cell (MLC) layers, such as triple-level cell (TLC) layers, provide for a coupled SLC/MLC write operation where SLC write protection is combined into a MLC write flow. In an illustrative example, data is written concurrently to SLC and TLC. The SLC data provides a backup for the TLC data in the event the TLC data is defective. The TLC data is verified using, for example, write verification. If the data is successfully verified, the SLC block can be erased or otherwise overwritten with new data. If not, the SLC block can be used to recover the data for storage in a different TLC block. The coupled SLC/MLC write operation may be performed in conjunction with a quick pass write (QPW).

Abstract: Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

Abstract: In a method for address table cache management, a first logical address associated with a first read command may be received. The first logical address may be associated with a first segment of an address mapping table. A second logical address associated with a second read command may then be received. The second logical address may be associated with a second segment of the address mapping table. A correlation metric associating the first segment to the second segment may be increased in response to receiving the first logical address before the second logical address. The first logical address and second logical address may each map to a physical address within the address mapping table, and a mapping table cache may be configured to store two or more segments. The mapping table cache may then be managed based on the correlation metric.

Abstract: Disclosed are systems and methods for efficient power management for storage devices. A method includes receiving a request to transition a flash memory to a first stand-by mode, wherein the flash memory comprises a plurality of dies. The method also includes causing one or more guard dies of the plurality of dies to transition to the first stand-by mode while causing one or more other dies of the plurality of dies to transition to a second stand-by mode, wherein the second stand-by mode is configured to consume less power than the first stand-by mode. The method also includes receiving an input/output (I/O) request for the flash memory. The method also includes causing the I/O request to be performed on the one or more guard dies that are in the first stand-by mode but not in the second stand-by mode.

Abstract: Systems and methods for storing data are described. A system can comprise a controller, one or more physical non-volatile memory devices, a bus comprising a plurality of input/output (I/O) lines. The controller configured to receive data, encode the received data into a codeword, and transfer, in parallel, different portions of the codeword to different physical non-volatile memory devices among the plurality of physical non-volatile memory devices.