Patents by Inventor Tomer Ziv

Tomer Ziv has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10474216
    Abstract: A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: November 12, 2019
    Assignee: INTEL CORPORATION
    Inventors: Doron Rajwan, Dorit Shapira, Itai Feit, Nadav Shulman, Efraim (Efi) Rotem, Tal Kuzi, Eliezer Weissmann, Tomer Ziv, Nir Rosenzweig
  • Publication number: 20190209827
    Abstract: According to a preferred embodiment of the present invention there is provided a stopcock including a housing element defining at least first, second and third ports, a handle element which is selectably positionable relative to the housing element, at least one fluid passageway communicating between at least two of the at least first, second and third ports, the at least one fluid passageway being selectably defined by at least one of the housing element and the handle element, the at least one fluid passageway being configured for enabling flushing an internal volume of at least one of the first, second and third ports by a fluid flow which does not flow entirely through the port whose internal volume is being flushed.
    Type: Application
    Filed: March 19, 2019
    Publication date: July 11, 2019
    Inventors: David Ziv, Tomer Gil
  • Patent number: 10222851
    Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: March 5, 2019
    Assignee: INTEL CORPORATION
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Nadav Shulman, Gal Leibovich, Tomer Ziv, Amit Gabai, Jorge P. Rodriguez, Jeffrey A. Carlson
  • Publication number: 20180059748
    Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.
    Type: Application
    Filed: September 13, 2017
    Publication date: March 1, 2018
    Inventors: Nir Rosenzweig, Doron Rajwan, Dorit Shapira, Nadav Shulman, Tomer Ziv
  • Patent number: 9864667
    Abstract: Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 9, 2018
    Assignee: Intel Corporation
    Inventors: Doron Rajwan, Eliezer Weissmann, Yoni Aizik, Itai Feit, Tal Kuzi, Tomer Ziv, Nadav Shulman
  • Patent number: 9791904
    Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Nir Rosenzweig, Doron Rajwan, Dorit Shapira, Nadav Shulman, Tomer Ziv
  • Publication number: 20170285703
    Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.
    Type: Application
    Filed: June 15, 2017
    Publication date: October 5, 2017
    Inventors: Israel Diamand, Asaf Rubinstein, Arik Gihon, Tal Kuzi, Tomer Ziv, Nadav Shulman
  • Patent number: 9710054
    Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 28, 2015
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Israel Diamand, Asaf Rubinstein, Arik Gihon, Tal Kuzi, Tomer Ziv, Nadav Shulman
  • Publication number: 20170177065
    Abstract: A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.
    Type: Application
    Filed: December 16, 2015
    Publication date: June 22, 2017
    Inventors: Doron Rajwan, Dorit Shapira, Itai Feit, Nadav Shulman, Efraim (Efi) Rotem, Tal Kuzi, Eliezer Weissmann, Tomer Ziv, Nir Rosenzweig
  • Publication number: 20170090945
    Abstract: Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Applicant: Intel Corporation
    Inventors: Doron Rajwan, Eliezer Weissmann, Yoni Aizik, Itai Feit, Tal Kuzi, Tomer Ziv, Nadav Shulman
  • Publication number: 20170038815
    Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
    Type: Application
    Filed: October 21, 2016
    Publication date: February 9, 2017
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Nadav Shulman, Gal Leibovich, Tomer Ziv, Amit Gabai, Jorge P. Rodriguez, Jeffrey A. Carlson
  • Patent number: 9477243
    Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Nadav Shulman, Gal Leibovich, Tomer Ziv, Amit Gabai, Jorge P. Rodriguez, Jeffrey A. Carlson
  • Publication number: 20160252952
    Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.
    Type: Application
    Filed: February 28, 2015
    Publication date: September 1, 2016
    Inventors: Israel Diamand, Asaf Rubinstein, Arik Gihon, Tal Kuzi, Tomer Ziv, Nadav Shulman
  • Publication number: 20160179110
    Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
    Type: Application
    Filed: December 22, 2014
    Publication date: June 23, 2016
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Nadav Shulman, Gal Leibovich, Tomer Ziv, Amit Gabai, Jorge P. Rodriguez, Jeffrey A. Carlson
  • Publication number: 20160048181
    Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.
    Type: Application
    Filed: August 15, 2014
    Publication date: February 18, 2016
    Inventors: Nir Rosenzweig, Doron Rajwan, Dorit Shapira, Nadav Shulman, Tomer Ziv
  • Patent number: 9235254
    Abstract: In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: January 12, 2016
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Tomer Ziv, Doron Rajwan, Efraim Rotem
  • Patent number: 9074947
    Abstract: In one embodiment, the present invention includes a method for determining if a core of a multicore processor is in a low power state, and if so, estimating a temperature of the core and storing the estimated temperature in a thermal storage area for the first core. By use of this estimated temperature, an appropriate voltage at which to operate the core when it exits the low power state can be determined. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Itai Feit, Tomer Ziv, Doron Rajwan, Nadav Shulman, Alon Naveh
  • Patent number: 8954770
    Abstract: In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: February 10, 2015
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishan, Tomer Ziv, Doron Rajwan, Efraim Rotem
  • Patent number: 8806248
    Abstract: With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: August 12, 2014
    Assignee: Intel Corporation
    Inventors: Jose P. Allarey, Varghese George, Sanjeev S. Jahagirdar, Oren Lamdan, Ofer Nathan, Tomer Ziv
  • Patent number: 8769323
    Abstract: With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: July 1, 2014
    Assignee: Intel Corporation
    Inventors: Jose P. Allarey, Varghese George, Sanjeev Jahagirdar, Oren Lamdan, Ofer Nathan, Tomer Ziv