Patents by Inventor Tomibumi INOUE

Tomibumi INOUE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8648453
    Abstract: In a POP type semiconductor device comprising a second semiconductor package as an upper package stacked on a first semiconductor package as a lower package, a plurality of main surface-side lands formed on a first wiring substrate of the first semiconductor package are disposed distributively on both sides of a chip mounting region as a boundary positioned at a central part of a main surface of the first wiring substrate, thus permitting the adoption of a through molding method. Consequently, a first sealing body formed on the main surface of the first wiring substrate in the first semiconductor package as a lower package extends from one second side of the first wiring substrate toward a central part of the other second side of the same substrate.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: February 11, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Minoru Shinohara, Tomibumi Inoue, Seiichiro Tsukui
  • Publication number: 20100181628
    Abstract: Prevention of disconnection of a bonding wire resulting from adhesive interface delamination between a resin and a leadframe, and improvement of joint strength of the resin and the leadframe are achieved in a device manufactured by a low-cost and simple processing. A boss is provided on a source lead by a stamping processing, and a support pillar is provided in a concave portion on a rear side of the source lead in order to prevent ultrasonic damping upon joining the bonding wire onto the boss, so that an insufficiency of the joint strength between the bonding wire and the source lead is prevented. Also, a continuous bump is provided on the boss so as to surround a joint portion between the source lead and the bonding wire, so that disconnection of the bonding wire resulting from delamination between the resin and the source lead is prevented.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 22, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Kenya Kawano, Kisho Ashida, Kuniharu Muto, Ichio Shimizu, Tomibumi Inoue
  • Publication number: 20100148350
    Abstract: In a POP type semiconductor device comprising a second semiconductor package as an upper package stacked on a first semiconductor package as a lower package, a plurality of main surface-side lands formed on a first wiring substrate of the first semiconductor package are disposed distributively on both sides of a chip mounting region as a boundary positioned at a central part of a main surface of the first wiring substrate, thus permitting the adoption of a through molding method. Consequently, a first sealing body formed on the main surface of the first wiring substrate in the first semiconductor package as a lower package extends from one second side of the first wiring substrate toward a central part of the other second side of the same substrate.
    Type: Application
    Filed: October 27, 2009
    Publication date: June 17, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Minoru SHINOHARA, Tomibumi INOUE, Seiichiro TSUKUI