Patents by Inventor Tomie Yamamoto

Tomie Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wiring pattern of semiconductor integrated circuit device
    Patent number: 5523627
    Abstract: As shown in FIG. 4, a wiring pattern of a semiconductor integrated circuit device of the present invention comprises a wiring portion extending from a connection hole and a connection portion located on the connection hole and having a matching allowance with respect to said connection hole on said wiring portion side being formed wider than a predetermined matching allowance by a predetermined width with which a required yield of successful matching can be assured.
    Type: Grant
    Filed: January 20, 1995
    Date of Patent: June 4, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Abe, Yasukazu Mase, Tomie Yamamoto
  • Method for patterning wirings of semiconductor integrated circuit device
    Patent number: 5411916
    Abstract: As shown in FIG. 4, a wiring pattern of a semiconductor integrated circuit device of the present invention comprises a wiring portion extending from a connection hole and a connection portion located on the connection hole and having a matching allowance with respect to said connection hole on said wiring portion side being formed wider than a predetermined matching allowance by a predetermined width with which a required yield of successful matching can be assured.
    Type: Grant
    Filed: March 18, 1993
    Date of Patent: May 2, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Abe, Yasukazu Mase, Tomie Yamamoto
  • Wiring pattern of semiconductor integrated circuit device
    Patent number: 5126819
    Abstract: As shown in FIG. 4, a wiring pattern of a semiconductor integrated circuit device of the present invention comprises a wiring portion extending from a connection hole and a connection portion located on the connection hole and having a matching allowance with respect to said connection hole on said wiring portion side being formed wider than a predetermined matching allowance by a predetermined width with which a required yield of successful matching can be assured.
    Type: Grant
    Filed: November 6, 1990
    Date of Patent: June 30, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Abe, Yasukazu Mase, Tomie Yamamoto
  • Semiconductor device having a composite insulating interlayer
    Patent number: 5055906
    Abstract: A semiconductor device has a first interconnection pattern formed on a semiconductor substrate, and a second interconnection pattern located in and over a through hole formed at a composite insulating layer structure. The composite insulating layer structure is constituted by a first inorganic insulating film and an organic insulating film. At a peripheral region of the second interconnection pattern, the organic insulating film is partially eliminated to form an eliminated portion. The semiconductor device also has a second inorganic insulating film which is formed over the organic insulating film and is directly formed on the first inorganic insulating film, via the eliminated portion.
    Type: Grant
    Filed: February 12, 1991
    Date of Patent: October 8, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasukazu Mase, Masahiro Abe, Tomie Yamamoto
  • Wiring pattern of semiconductor integrated circuit device
    Patent number: RE37059
    Abstract: As shown in FIG. 4, a wiring pattern of a semiconductor integrated circuit device of the present invention comprises a wiring portion extending from a connection hole and a connection portion located on the connection hole and having a matching allowance with respect to said connection hole on said wiring portion side being formed wider than a predetermined matching allowance by a predetermined width with which a required yield of successful matching can be assured.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: February 20, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Abe, Yasukazu Mase, Tomie Yamamoto