Patents by Inventor Tomihisa Hatano
Tomihisa Hatano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7694067Abstract: A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.Type: GrantFiled: January 16, 2008Date of Patent: April 6, 2010Assignee: Renesas Technology Corp.Inventors: Nagamasa Mizushima, Takashi Tsunehiro, Motoyasu Tsunoda, Toshio Tanaka, Kunihiro Katayama, Koichi Kimura, Tomihisa Hatano
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Patent number: 7607140Abstract: In a client/server architecture system, a device management system having the function of safely sharing a device without compromising user convenience is provided. The device is coupled to a terminal that the user uses or a hub coupled to a network. A device management manager having a device driver function and communication function installed on the terminal or the like, a virtual device manager having a device driver function and communication function installed on the server, and an authentication server that manages access permission for the device allow the device to be virtually available as in the case of the device directly coupled to the server while managing the access to the device.Type: GrantFiled: February 28, 2006Date of Patent: October 20, 2009Assignee: Hitachi, Ltd.Inventors: Takatoshi Kato, Takashi Tsunehiro, Tomihisa Hatano
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Publication number: 20090013125Abstract: A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.Type: ApplicationFiled: January 16, 2008Publication date: January 8, 2009Inventors: Nagamasa MIZUSHIMA, Takashi Tsunehiro, Motoyasu Tsunoda, Toshio Tanaka, Kunihiro Katayama, Koichi Kimura, Tomihisa Hatano
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Publication number: 20080120726Abstract: To provide a mechanism for preventing information leakage by erasing stored information if a preset condition is not satisfied, because if an external storage device in which the information is stored is stolen or lost the risk of information leakage through decryption still remains even in the case where the information is encrypted. An external storage device has a locking management function capable of setting available conditions for stored information and controlling permission/prohibition of user access depending on whether the conditions are satisfied. User access is permitted if the available conditions are satisfied. The stored information is erased if the available conditions are not satisfied.Type: ApplicationFiled: September 28, 2007Publication date: May 22, 2008Inventors: Takashi Tsunehiro, Hiromi Isokawa, Tomihisa Hatano, Takatoshi Kato
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Patent number: 7350023Abstract: A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip, wherein, the flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.Type: GrantFiled: December 11, 2006Date of Patent: March 25, 2008Assignee: Renesas Technology Corp.Inventors: Nagamasa Mizushima, Takashi Tsunehiro, Motoyasu Tsunoda, Toshio Tanaka, Kunihiro Katayama, Koichi Kimura, Tomihisa Hatano
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Publication number: 20070088906Abstract: A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip, wherein, the flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.Type: ApplicationFiled: December 11, 2006Publication date: April 19, 2007Inventors: Nagamasa Mizushima, Takashi Tsunehiro, Motoyasu Tsunoda, Toshio Tanaka, Kunihiro Katayama, Koichi Kimura, Tomihisa Hatano
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Patent number: 7185145Abstract: It is an object of the invention to improve security of a storage apparatus. The invention has: a flash memory chip; an IC card chip which can execute a security process (encryption, decryption, etc.); and a controller chip for controlling read/write of data from/into the flash memory chip and the IC card chip in response to a request from a host.Type: GrantFiled: May 29, 2002Date of Patent: February 27, 2007Assignee: Renesas Technology Corp.Inventors: Nagamasa Mizushima, Takashi Tsunehiro, Motoyasu Tsunoda, Toshio Tanaka, Kunihiro Katayama, Koichi Kimura, Tomihisa Hatano
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Publication number: 20070011446Abstract: In a client/server architecture system, a device management system having the function of safely sharing a device without compromising user convenience is provided. The device is coupled to a terminal that the user uses or a hub coupled to a network. A device management manager having a device driver function and communication function installed on the terminal or the like, a virtual device manager having a device driver function and communication function installed on the server, and an authentication server that manages access permission for the device allow the device to be virtually available as in the case of the device directly coupled to the server while managing the access to the device.Type: ApplicationFiled: February 28, 2006Publication date: January 11, 2007Inventors: Takatoshi Kato, Takashi Tsunehiro, Tomihisa Hatano
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Publication number: 20040177215Abstract: It is an object of the invention to improve security of a storage apparatus. The invention has: a flash memory chip; an IC card chip which can execute a security process (encryption, decryption, etc.); and a controller chip for controlling read/write of data from/into the flash memory chip and the IC card chip in response to a request from a host.Type: ApplicationFiled: May 12, 2004Publication date: September 9, 2004Inventors: Mizushima Nagamasa, Takashi Tsunehiro, Motoyasu Tsunoda, Toshio Tanaka, Kunihiro Katayama, Koichi Kimura, Tomihisa Hatano
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Patent number: 6459644Abstract: In the present invention, disclosed is a semiconductor memory device capable of reducing the number of erasing times of each block allocated to a cluster or the number of blocks to be erased in one writing to the minimum. As an embodiment of the present invention, when a host system 1 performs accessing, for each cluster as a unit, to the FAT partition prepared on a flash memory 17 of the semiconductor memory device 100, a CPU 6 adds an address offset value held by address offset storage section 10 to a logical address specified by the host system 1, whereby a logical address of a head sector of the cluster correspond to a physical address of a head sector of a unit block for erasing/writing data in the flash memory 17.Type: GrantFiled: February 9, 2001Date of Patent: October 1, 2002Assignee: Hitachi, Ltd.Inventors: Nagamasa Mizushima, Kunihiro Katayama, Kazunori Furusawa, Tomihisa Hatano, Takayuki Tamura
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Publication number: 20010048121Abstract: In the present invention, disclosed is a semiconductor memory device capable of reducing the number of erasing times of each block allocated to a cluster or the number of blocks to be erased in one writing to the minimum. As an embodiment of the present invention, when a host system 1 performs accessing, for each cluster as a unit, to the FAT partition prepared on a flash memory 17 of the semiconductor memory device 100, a CPU 6 adds an address offset value held by address offset storage section 10 to a logical address specified by the host system 1, whereby a logical address of a head sector of the cluster corresponds to a physical address of a head sector of a unit block for erasing/writing data in the flash memory 17.Type: ApplicationFiled: February 9, 2001Publication date: December 6, 2001Inventors: Nagamasa Mizushima, Kunihiro Katayama, Kazunori Furusawa, Tomihisa Hatano, Takayuki Tamura
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Patent number: 5644404Abstract: A facsimile receiving processing unit in a facsimile server terminal receives and stores facsimile data in a data storage unit. A receiving-end user issues a request for accessing the received facsimile data stored in the data storage unit through a received facsimile accessing unit in a client terminal to a received facsimile manager in the facsimile server terminal. At the time when the received facsimile data is accessed for the first time, a response data creating unit in the facsimile server terminal automatically creates response data which indicates that the facsimile data has been accessed at the receiving end, and then the response data is sent back to the sending-end facsimile machine by a facsimile transmission processing unit in the facsimile server terminal. This allows the sending-end user to recognize whether the facsimile data has actually been accessed by the receiving-end user.Type: GrantFiled: September 6, 1994Date of Patent: July 1, 1997Assignee: Hitachi, Ltd.Inventors: Shin'ichi Hashimoto, Tomihisa Hatano, Kazuhiro Umemura, Hiroshi Kawamura