Patents by Inventor Tomihisa Hatano

Tomihisa Hatano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7694067
    Abstract: A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Nagamasa Mizushima, Takashi Tsunehiro, Motoyasu Tsunoda, Toshio Tanaka, Kunihiro Katayama, Koichi Kimura, Tomihisa Hatano
  • Patent number: 7607140
    Abstract: In a client/server architecture system, a device management system having the function of safely sharing a device without compromising user convenience is provided. The device is coupled to a terminal that the user uses or a hub coupled to a network. A device management manager having a device driver function and communication function installed on the terminal or the like, a virtual device manager having a device driver function and communication function installed on the server, and an authentication server that manages access permission for the device allow the device to be virtually available as in the case of the device directly coupled to the server while managing the access to the device.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: October 20, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Takatoshi Kato, Takashi Tsunehiro, Tomihisa Hatano
  • Publication number: 20090013125
    Abstract: A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.
    Type: Application
    Filed: January 16, 2008
    Publication date: January 8, 2009
    Inventors: Nagamasa MIZUSHIMA, Takashi Tsunehiro, Motoyasu Tsunoda, Toshio Tanaka, Kunihiro Katayama, Koichi Kimura, Tomihisa Hatano
  • Publication number: 20080120726
    Abstract: To provide a mechanism for preventing information leakage by erasing stored information if a preset condition is not satisfied, because if an external storage device in which the information is stored is stolen or lost the risk of information leakage through decryption still remains even in the case where the information is encrypted. An external storage device has a locking management function capable of setting available conditions for stored information and controlling permission/prohibition of user access depending on whether the conditions are satisfied. User access is permitted if the available conditions are satisfied. The stored information is erased if the available conditions are not satisfied.
    Type: Application
    Filed: September 28, 2007
    Publication date: May 22, 2008
    Inventors: Takashi Tsunehiro, Hiromi Isokawa, Tomihisa Hatano, Takatoshi Kato
  • Patent number: 7350023
    Abstract: A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip, wherein, the flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: March 25, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Nagamasa Mizushima, Takashi Tsunehiro, Motoyasu Tsunoda, Toshio Tanaka, Kunihiro Katayama, Koichi Kimura, Tomihisa Hatano
  • Publication number: 20070088906
    Abstract: A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip, wherein, the flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.
    Type: Application
    Filed: December 11, 2006
    Publication date: April 19, 2007
    Inventors: Nagamasa Mizushima, Takashi Tsunehiro, Motoyasu Tsunoda, Toshio Tanaka, Kunihiro Katayama, Koichi Kimura, Tomihisa Hatano
  • Patent number: 7185145
    Abstract: It is an object of the invention to improve security of a storage apparatus. The invention has: a flash memory chip; an IC card chip which can execute a security process (encryption, decryption, etc.); and a controller chip for controlling read/write of data from/into the flash memory chip and the IC card chip in response to a request from a host.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: February 27, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Nagamasa Mizushima, Takashi Tsunehiro, Motoyasu Tsunoda, Toshio Tanaka, Kunihiro Katayama, Koichi Kimura, Tomihisa Hatano
  • Publication number: 20070011446
    Abstract: In a client/server architecture system, a device management system having the function of safely sharing a device without compromising user convenience is provided. The device is coupled to a terminal that the user uses or a hub coupled to a network. A device management manager having a device driver function and communication function installed on the terminal or the like, a virtual device manager having a device driver function and communication function installed on the server, and an authentication server that manages access permission for the device allow the device to be virtually available as in the case of the device directly coupled to the server while managing the access to the device.
    Type: Application
    Filed: February 28, 2006
    Publication date: January 11, 2007
    Inventors: Takatoshi Kato, Takashi Tsunehiro, Tomihisa Hatano
  • Publication number: 20040177215
    Abstract: It is an object of the invention to improve security of a storage apparatus. The invention has: a flash memory chip; an IC card chip which can execute a security process (encryption, decryption, etc.); and a controller chip for controlling read/write of data from/into the flash memory chip and the IC card chip in response to a request from a host.
    Type: Application
    Filed: May 12, 2004
    Publication date: September 9, 2004
    Inventors: Mizushima Nagamasa, Takashi Tsunehiro, Motoyasu Tsunoda, Toshio Tanaka, Kunihiro Katayama, Koichi Kimura, Tomihisa Hatano
  • Patent number: 6459644
    Abstract: In the present invention, disclosed is a semiconductor memory device capable of reducing the number of erasing times of each block allocated to a cluster or the number of blocks to be erased in one writing to the minimum. As an embodiment of the present invention, when a host system 1 performs accessing, for each cluster as a unit, to the FAT partition prepared on a flash memory 17 of the semiconductor memory device 100, a CPU 6 adds an address offset value held by address offset storage section 10 to a logical address specified by the host system 1, whereby a logical address of a head sector of the cluster correspond to a physical address of a head sector of a unit block for erasing/writing data in the flash memory 17.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: October 1, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Nagamasa Mizushima, Kunihiro Katayama, Kazunori Furusawa, Tomihisa Hatano, Takayuki Tamura
  • Publication number: 20010048121
    Abstract: In the present invention, disclosed is a semiconductor memory device capable of reducing the number of erasing times of each block allocated to a cluster or the number of blocks to be erased in one writing to the minimum. As an embodiment of the present invention, when a host system 1 performs accessing, for each cluster as a unit, to the FAT partition prepared on a flash memory 17 of the semiconductor memory device 100, a CPU 6 adds an address offset value held by address offset storage section 10 to a logical address specified by the host system 1, whereby a logical address of a head sector of the cluster corresponds to a physical address of a head sector of a unit block for erasing/writing data in the flash memory 17.
    Type: Application
    Filed: February 9, 2001
    Publication date: December 6, 2001
    Inventors: Nagamasa Mizushima, Kunihiro Katayama, Kazunori Furusawa, Tomihisa Hatano, Takayuki Tamura
  • Patent number: 5644404
    Abstract: A facsimile receiving processing unit in a facsimile server terminal receives and stores facsimile data in a data storage unit. A receiving-end user issues a request for accessing the received facsimile data stored in the data storage unit through a received facsimile accessing unit in a client terminal to a received facsimile manager in the facsimile server terminal. At the time when the received facsimile data is accessed for the first time, a response data creating unit in the facsimile server terminal automatically creates response data which indicates that the facsimile data has been accessed at the receiving end, and then the response data is sent back to the sending-end facsimile machine by a facsimile transmission processing unit in the facsimile server terminal. This allows the sending-end user to recognize whether the facsimile data has actually been accessed by the receiving-end user.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: July 1, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Shin'ichi Hashimoto, Tomihisa Hatano, Kazuhiro Umemura, Hiroshi Kawamura