Patents by Inventor Tomiji Sato

Tomiji Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LSI package and internal connecting method used therefor
    Patent number: 6653168
    Abstract: The present invention is provides an LSI package without employing steps for forming solder bumps on a bare chip and soldering to an interposer. In the present invention, a bare chip is mounted on the LSI package by forming wiring patterns which connect to bare chip I/O terminals in a build-up layer of a substrate. Furthermore, the wiring patterns are formed so as to connect outer I/O terminals on the substrate.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: November 25, 2003
    Assignee: NEC Corporation
    Inventors: Hitoshi Hoshino, Tomiji Sato, Atsushi Taga
  • LSI package and internal connecting method used therefor
    Publication number: 20030122234
    Abstract: The present invention is provides an LSI package without employing steps for forming solder bumps on a bare chip and soldering to an interposer. In the present invention, a bare chip is mounted on the LSI package by forming wiring patterns which connect to bare chip I/O terminals in a build-up layer of a substrate. Furthermore, the wiring patterns are formed so as to connect outer I/O terminals on the substrate.
    Type: Application
    Filed: February 10, 2003
    Publication date: July 3, 2003
    Applicant: NEC CORPORATION
    Inventors: Hitoshi Hoshino, Tomiji Sato, Atsushi Taga
  • LSI package with internal wire patterns to connect and mount bare chip to substrate
    Patent number: 6538310
    Abstract: The present invention is provides an LSI package without employing steps for forming solder bumps on a bare chip and soldering to an interposer. In the present invention, a bare chip is mounted on the LSI package by forming wiring patterns which connect to bare chip I/O terminals in a build-up layer of a substrate. Furthermore, the wiring patterns are formed so as to connect outer I/O terminals on the substrate.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: March 25, 2003
    Assignee: NEC Corporation
    Inventors: Hitoshi Hoshino, Tomiji Sato, Atsushi Taga
  • LSI package and internal connecting method used therefor
    Publication number: 20010050426
    Abstract: The present invention is provides an LSI package without employing steps for forming solder bumps on a bare chip and soldering to an interposer. In the present invention, a bare chip is mounted on the LSI package by forming wiring patterns which connect to bare chip I/O terminals in a build-up layer of a substrate. Furthermore, the wiring patterns are formed so as to connect outer I/O terminals on the substrate.
    Type: Application
    Filed: March 14, 2001
    Publication date: December 13, 2001
    Inventors: Hitoshi Hoshino, Tomiji Sato, Atsushi Taga