Patents by Inventor Tomio Aida

Tomio Aida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7317904
    Abstract: A DC offset cancel circuit includes an analog adder 1 to whose one input a baseband analog signal output from a high-frequency reception section is input and to whose other input an analog correction signal output from a D/A converter 7 is input, and which corrects the reference voltage value of the baseband analog signal analogically to cancel a DC offset, an adder 3 which has the output of the A/D converter 2 as its one input and subtracts the lower bits of a sample value stored in a memory 6 to be described later as a DC offset value from the input value and outputs the resultant value, a control circuit 5 which outputs an output digital value of the A/D converter 2 as a sample value to the memory 6, and a D/A converter 7 which converts a digital value of the upper bits of a sample value stored in the memory 6 to an analog correction signal and outputs the analog correction signal to the analog adder 1.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: January 8, 2008
    Assignee: Matshushita Electric Industrial Co., Ltd.
    Inventors: Masatoshi Matsushita, Tomio Aida, Yasutaka Uramoto
  • Publication number: 20050143032
    Abstract: A DC offset cancel circuit includes an analog adder 1 to whose one input a baseband analog signal output from a high-frequency reception section is input and to whose other input an analog correction signal output from a D/A converter 7 is input, and which corrects the reference voltage value of the baseband analog signal analogically to cancel a DC offset, an adder 3 which has the output of the A/D converter 2 as its one input and subtracts the lower bits of a sample value stored in a memory 6 to be described later as a DC offset value from the input value and outputs the resultant value, a control circuit 5 which outputs an output digital value of the A/D converter 2 as a sample value to the memory 6, and a D/A converter 7 which converts a digital value of the upper bits of a sample value stored in the memory 6 to an analog correction signal and outputs the analog correction signal to the analog adder 1.
    Type: Application
    Filed: December 22, 2004
    Publication date: June 30, 2005
    Inventors: Masatoshi Matsushita, Tomio Aida, Yasutaka Uramoto