Abstract: DAC includes a reference current setting unit (RCSU) that sets reference current, and current cell output unit (CCOU) including plurality of current sources, the current sources being configured to output currents corresponding to the reference current, the CCOU being configured to generate analog voltage signal according to an input digital signal, wherein the RCSU includes, reference current source (RCS) that generates the reference current, first and second resistance through which the reference current flows, selection control circuit that, when amplitude level of the analog voltage signal is to be changed, selects at least one of the first and second resistances and connect the selected resistance to the RCS, and reference current control circuit that controls current amount of reference current of the RCS according to voltage generated by resistance selected from among the first and second resistances.

Abstract: DAC includes a reference current setting unit (RCSU) that sets reference current, and current cell output unit (CCOU) including plurality of current sources, the current sources being configured to output currents corresponding to the reference current, the CCOU being configured to generate analog voltage signal according to an input digital signal, wherein the RCSU includes, reference current source (RCS) that generates the reference current, first and second resistance through which the reference current flows, selection control circuit that, when amplitude level of the analog voltage signal is to be changed, selects at least one of the first and second resistances and connect the selected resistance to the RCS, and reference current control circuit that controls current amount of reference current of the RCS according to voltage generated by resistance selected from among the first and second resistances.

Abstract: A bipolar transistor is provided with a collector layer of a first conductive type, a base layer of a second conductive type formed at a surface of the collector layer, and an emitter layer of the first conductive type formed at a surface of the base layer. An emitter electrode is connected to the emitter layer. Base electrodes are connected to the base layer and surround the emitter electrode. Emitter electrodes are connected to the collector layer and surround the base electrodes.

Abstract: A reference voltage supply circuit is provided with a PNP transistor. The PNP transistor has an N-type well for a base formed at a surface of a P-type semiconductor substrate. The reference voltage supply circuit is further provided with a resistor element connected to an emitter of the PNP transistor. The resistor element has an N-type well for a resistor at the surface of the P-type semiconductor substrate. The well is fabricated at the same time as when the N-type well for a base is fabricated.

Abstract: A reference voltage supply circuit is provided with a PNP transistor. The PNP transistor has an N-type well for a base formed at a surface of a P-type semiconductor substrate. The reference voltage supply circuit is further provided with a resistor element connected to an emitter of the PNP transistor. The resistor element has an N-type well for a resistor at the surface of the P-type semiconductor substrate. The well is fabricated at the same time as when the N-type well for a base is fabricated.

Abstract: A bipolar transistor is provided with a collector layer of a first conductive type, a base layer of a second conductive type formed at a surface of the collector layer, and an emitter layer of the first conductive type formed at a surface of the base layer. An emitter electrode is connected to the emitter layer. Base electrodes are connected to the base layer and surround the emitter electrode. Emitter electrodes are connected to the collector layer and surround the base electrodes.

Abstract: A reference voltage supply circuit is provided with a PNP transistor. The PNP transistor has an N-type well for a base formed at a surface of a P-type semiconductor substrate. The reference voltage supply circuit is further provided with a resistor element connected to an emitter of the PNP transistor. The resistor element has an N-type well for a resistor at the surface of the P-type semiconductor substrate. The well is fabricated at the same time as when the N-type well for a base is fabricated.

Abstract: The different signal generation circuit has a first transistor MP2 connected between a first power supply line Vcc and a first output terminal OTP and a gate connected to a first node, a second transistor MN2 connected between the first output terminal OTP and a second power supply line GND and a gate connected to a second node, and a delay circuit 31 and 13 connected between the first node and the second node.

Abstract: The D/A converting device disclosed includes a decoder, and a plurality of unit current generating circuits each having a differential switching circuit and a reference voltage generating circuit. The decoder receives a digital input value of n bits and outputs a plurality of complementary pairs of digital signals corresponding to the n bits of the digital input value. Each unit current generating circuit receives a complementary pair of digital signals from the decoder. The differential switching circuit has two complementary current output terminals, a bias voltage input and a reference voltage input. The two complementary current output terminals of the differential switching circuit are interconnected between corresponding ones of the unit current generating circuits with the interconnected points being made two complementary analog output terminals.

Abstract: A constant current source is connected to a first node that connects on the one hand to a predetermined potential via a first switching transistor with a control electrode thereof connected to a signal input terminal, a second node, and a resistive conduction member, and on the other hand to a current output terminal via a second switching transistor with a control electrode thereof connected to the second node to constitute a current switching circuit operable without an external reference bias and with a reduced number of components.

Abstract: A digital-to-analog converter having a main analog conversion part which carries out digital to analog conversion of input digital signals, an auxiliary analog conversion part which compensates the digital-to-analog conversion error, a memory circuit which accumulates the compensation data for compensating the conversion error, a register circuit which inputs the output signal of the memory circuit, and a matrix switching circuit which selects the output signal of the register circuit by means of the higher order bits of the input digital signal.Prior to the start of the digital-to-analog conversion operation the compensation data accumulated in the memory circuit are transferred to the register circuit. Later, at the time of the digital to analog conversion operation the matrix switching circuit is controlled by means of the higher order bits of the input digital signal selects the data held in the register circuit, and carries out the compensation of the error in the analog conversion.