Patents by Inventor Tomio Ueda

Tomio Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8466749
    Abstract: A variable gain amplifier includes a source-grounded transistor, to a gate of which an input signal is supplied; a plurality of first cascode transistors, sources of which are connected to a drain of the source-grounded transistor; a second cascode transistor, a source of which is connected to the drain of the source-grounded transistor; a first gate-grounded transistor, a source of which is connected to drains of the plurality of first cascode transistors, and to a gate of which a constant voltage is applied; and an output load connected to a drain of the first gate-grounded transistor wherein the plurality of first cascode transistors and the second cascade transistor are put into a conducting state or a non-conducting state such that a drain current of the source-grounded transistor is constant and moreover a fraction of the drain current supplied to the plurality of first cascade transistors changes.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: June 18, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Jungwuk Ahn, Teppei Suda, Tomio Ueda
  • Publication number: 20120105157
    Abstract: A variable gain amplifier includes a source-grounded transistor, to a gate of which an input signal is supplied; a plurality of first cascode transistors, sources of which are connected to a drain of the source-grounded transistor; a second cascode transistor, a source of which is connected to the drain of the source-grounded transistor; a first gate-grounded transistor, a source of which is connected to drains of the plurality of first cascode transistors, and to a gate of which a constant voltage is applied; and an output load connected to a drain of the first gate-grounded transistor wherein the plurality of first cascode transistors and the second cascade transistor are put into a conducting state or a non-conducting state such that a drain current of the source-grounded transistor is constant and moreover a fraction of the drain current supplied to the plurality of first cascade transistors changes.
    Type: Application
    Filed: August 23, 2011
    Publication date: May 3, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Jungwuk AHN, Teppei SUDA, Tomio UEDA
  • Patent number: 6232816
    Abstract: A signal level monitoring circuit for outputting either voltage or current corresponding to an input signal level, includes a variable gain unit for obtaining a predetermined output level without being dependent on a gain, when the input signal level is a predetermined reference input level; and an offset adding unit for outputting a predetermined reference output level by adding an offset level to the output level of the variable gain means, when the input signal level is the predetermined reference input level. According to the present invention, it is possible to adjust precisely and surely the gain and the offset voltage based on simple adjusting steps in a short time and only once.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: May 15, 2001
    Assignee: Fujitsu Limited
    Inventor: Tomio Ueda
  • Patent number: 5515008
    Abstract: An output level automatic control apparatus suitable for use to keep a transmitted output level of a radio system constant has an objective to prevent an output level above a specified value from being transmitted if an input level abruptly becomes a normal level from a break state, and to stabilize the output level with a simple configuration. The output level automatic control apparatus includes a main amplifier output level feed-back control loop extending from an output side of a main amplifier to a variable attenuator, which main amplifier output level feed-back control loop includes an output level detecting means, a reference value setting means, and a control means controlling the variable attenuator on the basis of a result obtained by comparing a detected output of the main amplifier with a reference value.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: May 7, 1996
    Assignee: Fujitsu Limited
    Inventors: Tomio Ueda, Kenichi Sato
  • Patent number: 5034702
    Abstract: Disclosed is an amplifying circuit comprising an amplifying transistor for amplifying an input signal, and a bias circuit for determining a current passing through the amplifying transistor and for determining an output voltage at the output of the amplifying transistor. The bias circuit comprising a current determining transistor for determining a current conducting through the amplifying transistor and a voltage determining transistor for determining an output voltage at the output of the amplifying transistor. The output voltage is determined independently from the determination of the current.
    Type: Grant
    Filed: February 14, 1990
    Date of Patent: July 23, 1991
    Assignee: Fujitsu Limited
    Inventor: Tomio Ueda