Abstract: A semiconductor device including a Horizontal Current Bipolar Transistor (HCBT) and methods of manufacture. The device has a semiconductor substrate of a first conductivity type defining a wafer plane parallel to the semiconductor substrate and has a base region and a collector region forming a first metallurgical junction. The device also has an emitter region forming a second metallurgical junction with the base region. A flat portion of the first metallurgical junction and a flat portion of the second metallurgical junction are substantially parallel to each other and close an acute angle with the wafer plane. At least a portion of the base region comprises silicon-germanium alloy or silicon-germanium-carbon alloy.

Abstract: A semiconductor device including a Horizontal Current Bipolar Transistor (HCBT) and methods of manufacture. The device has a semiconductor substrate of a first conductivity type defining a wafer plane parallel to the semiconductor substrate and has a base region and a collector region forming a first metallurgical junction. The device also has an emitter region forming a second metallurgical junction with the base region. A flat portion of the first metallurgical junction and a flat portion of the second metallurgical junction are substantially parallel to each other and close an acute angle with the wafer plane. At least a portion of the base region comprises silicon-germanium alloy or silicon-germanium-carbon alloy.

Abstract: A semiconductor device including a Horizontal Current Bipolar Transistor (HCBT) and methods of manufacture. The device has a semiconductor substrate of a first conductivity type defining a wafer plane parallel to the semiconductor substrate and has a base region and a collector region forming a first metallurgical junction. The device also has an emitter region forming a second metallurgical junction with the base region. A flat portion of the first metallurgical junction and a flat portion of the second metallurgical junction are substantially parallel to each other and close an acute angle with the wafer plane. At least a portion of the base region comprises silicon-germanium alloy or silicon-germanium-carbon alloy.

Abstract: A horizontal current bipolar transistor comprises; an n-hill layer on a substrate, forming a first pn-junction with the substrate; a n+ diffusion layer on the substrate, adjacent to the n-hill layer, forming a n+n junction with the n-hill layer; an intrinsic base layer on the n-hill layer and comprising a portion of a sidewall inclined at an acute angle to the substrate plane, forming a second pn-junction with the n-hill layer; an extrinsic base layer on the n-hill layer, forming a third pn-junction with the n-hill layer, and a p+p junction with the intrinsic base layer; a field limiting region on the n-hill layer, forming a fourth pn-junction with the n-hill layer. The field limiting region is spatially separated from the extrinsic base layer and the n+ diffusion layer. The extrinsic base layer and the field limiting region exhibit substantially equal impurity dopant distribution decay towards the substrate.

Abstract: A horizontal current bipolar transistor comprises; an n-hill layer on a substrate, forming a first pn-junction with the substrate; a n+ diffusion layer on the substrate, adjacent to the n-hill layer, forming a n+n junction with the n-hill layer; an intrinsic base layer on the n-hill layer and comprising a portion of a sidewall inclined at an acute angle to the substrate plane, forming a second pn-junction with the n-hill layer; an extrinsic base layer on the n-hill layer, forming a third pn-junction with the n-hill layer, and a p+p junction with the intrinsic base layer; a field limiting region on the n-hill layer, forming a fourth pn-junction with the n-hill layer. The field limiting region is spatially separated from the extrinsic base layer and the n+ diffusion layer. The extrinsic base layer and the field limiting region exhibit substantially equal impurity dopant distribution decay towards the substrate.

Abstract: A photodiode detector array comprises: a substrate comprising a front surface and a mounting surface; a first active region and a second active region, each of said first and second active regions being operatively configured to detect electromagnetic radiation in a wavelength range, and each of said first and second active regions being formed within said substrate and disposed proximate to said front surface; and a layer formed within said substrate and disposed proximal to said mounting surface, wherein said layer exhibits an electromagnetic wave absorption coefficient greater than or equal to 3×103 cm-1 in the wavelength range from 500 nm to 800 nm.

Abstract: A horizontal current bipolar transistor comprises a substrate of first conductivity type, defining a wafer plane parallel to said substrate; a collector drift region above said substrate, having a second, opposite conductivity type, forming a first metallurgical pn-junction with said substrate; a collector contact region having second conductivity type above said substrate and adjacent to said collector drift region; a base region comprising a sidewall at an acute angle to said wafer plane, having first conductivity type, and forming a second metallurgical pn-junction with said collector drift region; and a buried region having first conductivity type between said substrate and said collector drift region forming a third metallurgical pn-junction with the collector drift region. An intercept between an isometric projection of said base region on said wafer plane and an isometric projection of said buried region on said wafer plane is smaller than said isometric projection of said base region.

Abstract: A horizontal current bipolar transistor comprises a substrate of first conductivity type, defining a wafer plane parallel to said substrate; a collector drift region above said substrate, having a second, opposite conductivity type, forming a first metallurgical pn-junction with said substrate; a collector contact region having second conductivity type above said substrate and adjacent to said collector drift region; a base region comprising a sidewall at an acute angle to said wafer plane, having first conductivity type, and forming a second metallurgical pn-junction with said collector drift region; and a buried region having first conductivity type between said substrate and said collector drift region forming a third metallurgical pn-junction with the collector drift region. An intercept between an isometric projection of said base region on said wafer plane and an isometric projection of said buried region on said wafer plane is smaller than said isometric projection of said base region.

Abstract: A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11. An emitter electrode 31A and a collector electrode 31B are formed in the open region 21 and are composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched.

Abstract: A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11. An emitter electrode 31A and a collector electrode 31B are formed in the open region 21 and are composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched.

Abstract: A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated therein. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11, an emitter electrode 31A and a collector electrode 31B each of which is formed in the open region 21 and is composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched to form the emitter electrode 31A and the collector electrode 31B.

Abstract: A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated therein. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11, an emitter electrode 31A and a collector electrode 31B each of which is formed in the open region 21 and is composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched to form the emitter electrode 31A and the collector electrode 31B.

Abstract: A bipolar transistor structure for use in integrated circuits where the active device is processed on the sidewall of an n-hill so that the surface footprint does not depend on the desired area of active device region (emitter area). This structure, which is referred to as a Horizontal Current Bipolar Transistor (HCBT), consumes a smaller area of chip surface than conventional devices, thereby enabling higher packing density of devices and/or the reduction of integrated circuit die size. The device is fabricated with a single polysilicon layer, without an epitaxial process, without demanding trench isolation technology, and with reduced thermal budget. Fabrication requires fewer etching processes and thermal oxidations than in conventional devices.

Abstract: A bipolar transistor structure for use in integrated circuits where the active device is processed on the sidewall of an n-hill so that the surface footprint does not depend on the desired area of active device region (emitter area). This structure, which is referred to as a Horizontal Current Bipolar Transistor (HCBT), consumes a smaller area of chip surface than conventional devices, thereby enabling higher packing density of devices and/or the reduction of integrated circuit die size. The device is fabricated with a single polysilicon layer, without an epitaxial process, without demanding trench isolation technology, and with reduced thermal budget. Fabrication requires fewer etching processes and thermal oxidations than in conventional devices.