Patents by Inventor Tomitaka Yamashita

Tomitaka Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6885962
    Abstract: An inspection process and method that is performed not by the operation of a PC but within the inspection device itself according to the inspection program stored in a memory circuit in the inspection device. Therefore, the inspection is performed without being affected by the performance of a PC with constant stability and reliability.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: April 26, 2005
    Assignee: Kabushiki Kaisha Moric
    Inventor: Tomitaka Yamashita
  • Publication number: 20020116142
    Abstract: An inspection process and method that is performed not by the operation of a PC but within the inspection device itself according to the inspection program stored in a memory circuit in the inspection device. Therefore, the inspection is performed without being affected by the performance of a PC with constant stability and reliability.
    Type: Application
    Filed: February 20, 2002
    Publication date: August 22, 2002
    Inventor: Tomitaka Yamashita
  • Patent number: 4906836
    Abstract: An integrated circuit includes an operational amplifier having inverting and noninverting input terminals, a first logarithmic amplifier having inverting and noninverting input terminals, and a second logarithmic amplifier having inverting and noninverting input terminals. The output of the first logarithmic amplifier is connected to the noninverting input terminal of the second logarithmic amplifier, and the output of the second logarithmic amplifier is connected to the inverting input terminal of the operational amplifier.
    Type: Grant
    Filed: September 23, 1988
    Date of Patent: March 6, 1990
    Assignee: Hamamatsu Photonics Kabushiki Kaisha
    Inventors: Tomitaka Yamashita, Mikio Kyomasu
  • Patent number: 4903103
    Abstract: A semiconductor photodiode device comprises a substrate with top and bottom opposite surfaces, having an upper portion of a first conductivity type adjacent the top surface and a lower portion of a second conductivity type adjacent the bottom surface, an anode region of the second conductivity type and a cathode region of the first conductivity type radially spaced from the anode region and disposed in the top surface of the substrate, and an isolation region of the second conductivity type disposed in the upper portion of the substrate radially spaced from the surrounding the cathode and anode regions. The isolation region extends to the lower portion of the substrate. A buried region of the first conductivity type underlies a portion of the top surface of the substrate enclosed by the cathode region and spaced from the anode, cathode and isolation regions such that the buried region is in contact with the upper and lower portions of the substrate.
    Type: Grant
    Filed: October 27, 1988
    Date of Patent: February 20, 1990
    Assignee: Hamamatsu Photonics Kabushiki Kaisha
    Inventors: Tomitaka Yamashita, Mikio Kyomasu