Patents by Inventor Tomiyasu Isago

Tomiyasu Isago has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160126750
    Abstract: A SS-method bidirectional contactless power supply device is arranged such that at the time of G2V, a second power converter converts commercial alternating current to direct current, a first power converter converts the direct current to high-frequency alternating current, and a third power converter converts the high-frequency alternating current to the direct current to charge an electric storage device. On driving the first power converter with a constant voltage, the electric storage device is charged with a constant current. At the time of V2G, the third power converter converts the direct current to the high-frequency alternating current, the first power converter converts the high-frequency alternating current to the direct current, and the second power converter converts the direct current to the commercial alternating current. On driving the third power converter with the constant current, an output of the first power converter becomes the constant voltage.
    Type: Application
    Filed: May 21, 2014
    Publication date: May 5, 2016
    Applicant: TECHNOVA INC.
    Inventors: Tomio YASUDA, Isami NORIGOE, Tomiyasu ISAGO
  • Patent number: 6717784
    Abstract: A rush current suppression circuit is used with a power supply circuit which includes a common line and an input voltage detection circuit and supplies power from an input power supply via a switching circuit. There is provided a smoothing capacitor coupled to an output end of the power supply circuit, and a rapid discharge and delay circuit coupled to the input voltage detection circuit and carrying out a rapid discharge and a time delay and controlling the switching circuit. The switching circuit includes two FETs which are coupled in series to the common line, and the two FETs have sources which are coupled to each other and gates which are coupled to each other and driven by the rapid discharge and delay circuit.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: April 6, 2004
    Assignee: Fujitsu Limited
    Inventors: Tomiyasu Isago, Naoki Takahashi, Yoshinori Usui, Tatsuo Araki
  • Publication number: 20030075988
    Abstract: A rush current suppression circuit is used with a power supply circuit which includes a common line and an input voltage detection circuit and supplies power from an input power supply via a switching circuit. There is provided a smoothing capacitor coupled to an output end of the power supply circuit, and a rapid discharge and delay circuit coupled to the input voltage detection circuit and carrying out a rapid discharge and a time delay and controlling the switching circuit. The switching circuit includes two FETs which are coupled in series to the common line, and the two FETs have sources which are coupled to each other and gates which are coupled to each other and driven by the rapid discharge and delay circuit.
    Type: Application
    Filed: March 26, 2002
    Publication date: April 24, 2003
    Inventors: Tomiyasu Isago, Naoki Takahashi, Yoshinori Usui, Tatsuo Araki
  • Patent number: 6304470
    Abstract: In a power supply device supplying, in parallel, power from a plurality of DC/DC converters to a common load, there is provided an output compensation circuit which is provided on an output side of each of the DC/DC converters and compensates for an output voltage drop due to a voltage drop developing across a diode for parallel operation.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: October 16, 2001
    Assignee: Fujitsu Limited
    Inventors: Tomiyasu Isago, Hiromitsu Ogawa