Abstract: Embodiments are directed towards a system on chip (SoC) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus, a plurality of addressable memory arrays coupled to the system bus, at least one applications processor core coupled to the system bus, and a configurable accelerator framework coupled to the system bus. The configurable accelerator framework is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus, wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework to execute the DCNN.

Abstract: In order to arbitrate competing requests made by master elements for shared resources in a data processing system in which the masters have controlled access to the resources through a communication bus, there is provided an arbitration unit coupled to the masters and to the resources through the communication bus. There is further provided logic structure in each master for generating and sending access request signals to the arbitration unit indicating that the master needs to direct, through the communication bus, a specified resource to perform an operation, the selected resource being identified by at last one of the access request signals. The arbitration unit, upon receiving the access request signal, arbitrates among competing access request signals, which may be concurrently received from a plurality of masters, according to predetermined priority criteria.

Abstract: In a data processing multiprocessor system having distributed shared resources where each system processor (7) is provided with at least a local memory (8) to which it get access through a local bus (11), and with an interface unit (10) for connection of the local bus (11) to a system bus (5) and wherein each of the system processors may have access the local memory of another processor through its own local bus, its own interface unit, the system bus and the local bus of the other processor, deadlock is prevented by providing a bypass unit (40) of the interface unit (10) for enabling access from the system bus to the local bus through the bypass unit, a block (9) connected between the local bus and the interface unit (10) for latching system bus access requests received from an agent processor on the local bus, and a block (12) for isolation of the agent processor outputs from local bus, so that each agent processor may post read/write operations in the related latching block (9) for latching bus access requ