Abstract: A multi-core system configured to execute a plurality of tasks and having a semaphore engine and a direct memory access (DMA) engine capable of selecting, by a task scheduler of a first core, a first task for execution by the first core. In response to a semaphore lock request, the task scheduler of the first core switches the first task to an inactive state and selects a next task for execution by the first core. After the semaphore engine acquires the semaphore lock of the first semaphore, a data transfer request is provided to the DMA engine. In response to the data transfer request, the DMA engine transfers data associated with the locked first semaphore to the entry of the workspace of the first core.

Abstract: A communication channel controller includes a queue, a memory map, and a scheduler. The queue to store a first memory transfer request received at the communication channel controller. The memory map stores information to identify a memory address range to be associated with a memory. The scheduler to compare a source address of the first memory transfer in the queue to the memory address range in the memory map to determine whether the source address of the first memory transfer request targets the memory, and in response allocate the first memory transfer request to a first communication channel of a plurality of communication channels in response to the first communication channel having all of its outstanding memory transactions to a common source address bank and source address page as a source address bank and a source address page of the first memory transfer request.

Abstract: A data processing device includes a plurality of devices, a processor core, a memory, and a queue manager. The processor core stores one or more commands in a command queue of the memory to be executed by the plurality of devices to implement a data transfer path. The queue manager stores a frame queue for each of the plurality of devices. Each frame queue includes a first field having a pointer to an address of the command queue, and a second field to identify a next-in-sequence frame queue. A first device stores a data descriptor in the frame queue of the second device to initiate a data transfer from the first device to the second device. The data descriptor includes a field to indicate an offset value from the address of the command queue to a location of a command to be executed by the second device.

Abstract: A source processor can divide each packet of a data stream into multiple segments prior to communication of the packet, allowing a packet to be transmitted in smaller chunks. The source processor can process the segments for two or more packets for a given data stream concurrently, and provide appropriate context information in each segments header to facilitate in order transmission and reception of the packets represented by the individual segments. Similarly, a destination processor can receive the packet segments packets for an ordered data stream from a source processor, and can assign different contexts, based upon the context information in each segments header. When a last segment is received for a particular packet, the context for the particular packet is closed, and a descriptor for the packet is sent to a queue. The order in which the last segments of the packets are transmitted maintains order amongst the packets.

Abstract: A thermal sensor system including at least one thermal sensor, a voltage control network, a current gain network, a current compare sensor, and a controller. The voltage control network applies reference and delta voltage levels to a thermal sensor, which develops reference and delta current signals. The current gain network is used to adjust current gain. The current compare sensor is responsive to the reference and delta current signals and provides a comparison metric. The controller selects a temperature subrange and controls the current gain network to adjust the gain of the delta current signal to determine a gain differential value indicative of the temperature. The controller may select from among different sized thermal sensors, current mode gain values, and control voltages corresponding with each of multiple temperature subranges. Any one or more of these parameters may be adjusted to adjust an operating point for selecting a corresponding temperature subrange.

Abstract: A method includes generating, by a first software process of the data processing system, a source partition descriptor for a DMA job which requires access to a first partition of a memory which is assigned to a second software process of the data processing system and not assigned to the first software process. The source partition descriptor comprises a partition identifier which identifies the first partition of the memory. The DMA unit receives the source partition descriptor and generates a destination partition descriptor for the DMA job. Generating the destination partition descriptor includes translating, by the DMA unit, the partition identifier to a buffer pool identifier which identifies a physical address within the first partition of the memory which is assigned to the second software process; and storing, by the DMA unit, the buffer pool identifier in the destination partition descriptor.

Abstract: A DMA controller allocates space at a buffer to different DMA engines based on the length of time data segments have been stored at a buffer. This allocation ensures that DMA engines associated with a destination that is experiencing higher congestion will be assigned less buffer space than a destination that is experiencing lower congestion. Further, the DMA controller is able to adapt to changing congestion conditions at the transfer destinations.

Abstract: A method includes generating, by a first software process of the data processing system, a source partition descriptor for a DMA job which requires access to a first partition of a memory which is assigned to a second software process of the data processing system and not assigned to the first software process. The source partition descriptor comprises a partition identifier which identifies the first partition of the memory. The DMA unit receives the source partition descriptor and generates a destination partition descriptor for the DMA job. Generating the destination partition descriptor includes translating, by the DMA unit, the partition identifier to a buffer pool identifier which identifies a physical address within the first partition of the memory which is assigned to the second software process; and storing, by the DMA unit, the buffer pool identifier in the destination partition descriptor.

Abstract: A method for controlling bandwidth in a direct memory access (DMA) unit of a computer processing system, the method comprising: assigning a DMA job to a selected DMA engine; starting a source timer; and issuing a request to read a next section of data for the DMA job. If a sufficient amount of the data was not obtained, allowing the DMA engine to wait until the source timer reaches a specified value before continuing to read additional data for the DMA job.

Abstract: A method for controlling bandwidth in a direct memory access (DMA) unit of a computer processing system, the method comprising: assigning a DMA job to a selected DMA engine; starting a source timer; and issuing a request to read a next section of data for the DMA job. If a sufficient amount of the data was not obtained, allowing the DMA engine to wait until the source timer reaches a specified value before continuing to read additional data for the DMA job.

Abstract: A method of multicast data transfer including accessing a source address to a source location of mapped memory which stores source data, accessing multiple destination addresses to corresponding destination locations of the mapped memory, and for each of at least one section of the source data, reading the section using the source address, storing the section into a local memory of a data transfer device, and writing the section from the local memory to each destination location in the mapped memory using the destination addresses. Separate source and destination attributes may be provided, so that the source and each destination may have different attributes for reading and storing data. The source and each destination may have any number of data buffers accessible by corresponding links provided in data structures supporting the data transfer. The source data may be divided into sections and handled section by section.