Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: A high intensity metal halide arc discharge lamp, such as an electrodeless lamp wherein RF energy is inductively coupled to the arc discharge, contains a halide of neodymium alone or in combination with other metals such as one or more rare earth metals, Na, Cs and is essentially mercury free (i.e., <1 mg per cc of arc chamber volume).

Abstract: A high intensity electrodeless metal halide arc discharge lamp wherein RF energy is coupled to the arc discharge, contains a halide of praseodymium alone or in combination with other metals such as one or more rare earth metals, Na and Cs and is essentially mercury free (i.e., < 1 mg per cc of arc chamber volume).

Abstract: The fill of a self-extinguishing gas probe starter for an electrodeless high intensity discharge lamp includes a starter fill component which has a relatively low vapor pressure and is substantially inert in the starter fill at ambient temperatures, but which component vaporizes and becomes electronegative as the temperature of the lamp increases, so that the starter fill component attaches electrons of the starting discharge in the gas probe starter and thereby extinguishes the starting discharge after initiation of the arc discharge in the arc tube. As a result, the flow of currents between the gas probe starter and the arc tube, which would otherwise have a detrimental effect on the arc tube wall, is avoided.

Abstract: A dual-sided test head for an integrated circuit test system. Each side of the test head has a floating contact surface which provides an electrical contact interface between one side of the test head and a respective load board. Each load board is part of a respective integrated circuit handling system. As the test head has two sides and a load board is contacted at each side, the floating contact surfaces facilitate docking of the test head to the respective load boards. The contactors are floating so as to have freedom of motion to rotate, tilt, offset laterally or offset vertically, relative to the test head.