Abstract: Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by reducing ARC loss during photoresist stripping associated with plural mask formation in the core memory cell region during patterning and ion implantations. Embodiments include sequentially etching the stacked gate electrode structure in the core memory cell region, photoresist stripping and etching to form the gate electrode structure in the peripheral circuitry region. Subsequently, plural maskings and ion implantations are implemented in the core memory cell region with attendant photoresist strippings.

Abstract: Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by avoiding ARC loss during photoresist stripping associated with plural maskings in the core memory cell region during patterning and ion implantations. Processing is simplified by employing the same mask in the memory cell region for patterning the stacked gate electrode structure and for ion implanting the shallow source/drain extensions. Embodiments include initially etching to form the gate electrode structure in the peripheral circuitry region. Subsequently, processing in the core memory cell region is conducted by etching the stacked gate electrode structure and ion implanting to form the source/drains with attendant stripping of photoresist layers.