Abstract: A method for fabricating buried channel NMOS devices and the devices themselves are disclosed. These buried channel NMOS devices are fabricated with a p-type substrate, an n-type implant in the top portion (approximately 400 to 1000 Å deep) of the substrate, and an insulating gate dielectric above the n-type implant. An n-type or p-type doped polysilicon gate electrode is formed on top of the insulating gate dielectric. The n-type implant region is doped in such a way that it is depleted of charge carriers when the device's gate electrode is at the same potential as the well (zero bias). When the gate electrode is biased +Ve with respect to the device's well substrate a conducting channel of mobile electrons is formed in a portion of the buried layer. This type of biasing is known as inversion bias since the charge carriers are of the opposite type than the p-well.

Abstract: A method and system for providing a semiconductor memory device is disclosed. The method and system include providing a plurality of gate stacks above a substrate. Each of the plurality of gate stacks includes a first edge and a second edge. The method and system also include providing a source implant adjacent to the first edge of each of the plurality of gate stacks and driving the source implant under the first edge of each of the plurality of gate stacks. The method and system also include providing a drain implant after source implant is driven under the first edge. The drain implant is in the substrate adjacent to the second edge of each of the plurality of gate stacks.

Abstract: A method and system for providing a semiconductor memory device is disclosed. The method and system include providing a plurality of gate stacks above a substrate. Each of the plurality of gate stacks includes a first edge and a second edge and crosses at least one field isolation region. The method and system also include providing a first source implant adjacent to the first edge of each of the plurality of gate stacks and driving the first source implant under the first edge of each of the plurality of gate stacks. The method and system also include providing a self-aligned source (SAS) etch that removes a portion of the at least one field isolation regions separating the plurality of source regions. The SAS etch is provided after the first source implant driving step. The method and system also include providing a first spacer and a second spacer for each of the plurality of gate stacks.

Abstract: A method and system for providing a semiconductor memory device is disclosed. The method and system include providing a plurality of gate stacks above a substrate. Each of the plurality of gate stacks includes a first edge and a second edge. The method and system also include providing a source implant adjacent to the first edge of each of the plurality of gate stacks and driving the source implant under the first edge of each of the plurality of gate stacks. The method and system also include providing a first spacer and a second spacer for each of the plurality of gate stacks. The first and second spacers are disposed along the first and second edges, respectively, of each of the plurality of gate stacks. The method and system also include providing a drain implant after source implant is driven under the first edge and after the first and second spacers are provided. The drain implant is in the substrate adjacent to the second spacer.