Abstract: Described herein are tetrahydro-pyrido[3,4-b]indol-1-yl compounds with estrogen receptor modulation activity or function having the Formula I structure: and stereoisomers, tautomers, or pharmaceutically acceptable salts thereof, and with the substituents and structural features described herein. Also described are pharmaceutical compositions and medicaments that include the Formula I compounds, as well as methods of using such estrogen receptor modulators, alone and in combination with other therapeutic agents, for treating diseases or conditions that are mediated or dependent upon estrogen receptors.

Abstract: Described herein are tetrahydro-pyrido[3,4-b]indol-1-yl compounds with estrogen receptor modulation activity or function having the Formula I structure: and stereoisomers, tautomers, or pharmaceutically acceptable salts thereof, and with the substituents and structural features described herein. Also described are pharmaceutical compositions and medicaments that include the Formula I compounds, as well as methods of using such estrogen receptor modulators, alone and in combination with other therapeutic agents, for treating diseases or conditions that are mediated or dependent upon estrogen receptors.

Abstract: Described herein are tetrahydro-pyrido[3,4-b]indol-1-yl compounds with estrogen receptor modulation activity or function having the Formula I structure: and stereoisomers, tautomers, or pharmaceutically acceptable salts thereof, and with the substituents and structural features described herein. Also described are pharmaceutical compositions and medicaments that include the Formula I compounds, as well as methods of using such estrogen receptor modulators, alone and in combination with other therapeutic agents, for treating diseases or conditions that are mediated or dependent upon estrogen receptors.

Abstract: Described herein are pyrimidinyl-pyridyloxy-naphthyl compounds with inositol requiring enzyme 1 (IRE1) modulation activity or function having the Formula I or I? structure: or stereoisomers, tautomers, or pharmaceutically acceptable salts thereof, and with the substituents and structural features described herein. Also described are pharmaceutical compositions and medicaments that include the Formula I or I? compounds, as well as methods of using such IRE1 modulators, alone and in combination with other therapeutic agents, for treating diseases or conditions that are mediated or dependent upon estrogen receptors.

Abstract: Described herein are pyrimidinyl-pyridyloxy-naphthyl compounds with inositol requiring enzyme 1 (IRE1) modulation activity or function having the Formula I or I? structure: or stereoisomers, tautomers, or pharmaceutically acceptable salts thereof, and with the substituents and structural features described herein. Also described are pharmaceutical compositions and medicaments that include the Formula I or I? compounds, as well as methods of using such IRE1 modulators, alone and in combination with other therapeutic agents, for treating diseases or conditions that are mediated or dependent upon estrogen receptors.

Abstract: Described herein are tetrahydro-pyrido[3,4-b]indol-1-yl compounds with estrogen receptor modulation activity or function having the Formula I structure: and stereoisomers, tautomers, or pharmaceutically acceptable salts thereof, and with the substituents and structural features described herein. Also described are pharmaceutical compositions and medicaments that include the Formula I compounds, as well as methods of using such estrogen receptor modulators, alone and in combination with other therapeutic agents, for treating diseases or conditions that are mediated or dependent upon estrogen receptors.

Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.

Abstract: An integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.

Abstract: An integrated circuit structure includes a semiconductor substrate and a thyristor formed thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

Abstract: A method of forming a power MOSFET having a substrate of a first conductivity type and a body region of a second conductivity type. The method includes the steps of forming a gate region of a pre-determined pattern and with a plurality of gate elements partially covering the substrate. The gate element has a stepped cross-sectional profile with a thicker portion and a thinner portion. The thicker portion is adapted to substantially prevent passage of impurities therethrough into the substrate during the impurities implantation step. The thinner portion is adapted to allow partial passage of impurities therethrough during the impurities implantation step. Impurities are implanted into the substrate from the gate region side of the substrate to form a body region of the second conductivity type.

Abstract: An integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.

Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.

Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.

Abstract: An integrated circuit structure includes a semiconductor substrate and a thyristor formed thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.

Abstract: Current practice of the common source configuration is to connect the sources of the two discrete MOSFETs (housed either in separated packages or in a single package) externally on the printed circuit board. Because the gate pads and source pads of the two dies are alternatively placed between gate and source, it does not allow the sources of the power MOSFETs to be connected internally, which requires an additional layer of circuit board to connect the sources and the gates externally. This invention provides a novel electronic device layout design and a novel packaging technique for common source configuration, placing two MOSFETs in a package with their sources connected to a single source post which is located between tow gate posts. In order to facilitate gate bonding and to prevent any shorting between gate and source, two gate pads are used and placed at the upper adjacent corners of each MOSFET.

Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a thyristor thereon. The thyristor has at least four layers, with three P—N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a thyristor thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.