Abstract: This invention describes a process for making a high density trench DMOS (Double-diffused Metal Oxide Semiconductor) transistor with improved gate oxide breakdown at the three-dimensional trench corners and better body contact which can improve the latch-up immunity and increase the drive current. A guard-ring mask is used to define a deep body to cover the three-dimensional trench corners, which can prevent early gate-oxide breakdown during the off-state operation. Another function of the guard-ring mask is to define self-aligned deeper trenches at the terminations of the trenches. The deeper trenches at the terminations of the trenches will result in thicker gate oxide grown at the terminations. This layer of thicker oxide is used to prevent the pre-mature gate oxide breakdown at the three-dimensional trench corners. A trench spacer is formed after the N-body drive-in step by depositing a layer of oxide and then followed by an oxide etch-back step.

Abstract: This invention describes a process for making a high density trench DMOS (Double-diffused Metal Oxide Semiconductor) transistor with improved gate oxide breakdown at the three-dimensional trench corners and better body contact which can improve the latch-up immunity and increase the drive current. A guard-ring mask is used to define a deep body to cover the three-dimensional trench corners, which can prevent early gate-oxide breakdown during the off-state operation. Another function of the guard-ring mask is to define self-aligned deeper trenches at the terminations of the trenches. The deeper trenches at the terminations of the trenches will result in thicker gate oxide grown at the terminations. This layer of thicker oxide is used to prevent the pre-mature gate oxide breakdown at the three-dimensional trench corners. A trench spacer is formed after the N-body drive-in step by depositing a layer of oxide and then followed by an oxide etch-back step.

Abstract: A new angle implant is provided that reduces or eliminates the effects of narrow channel impurity diffusion to surrounding regions of insulation. The invention provides for angle implantation of p-type impurities into corners of STI regions that are adjacent to NMOS devices and angle implantation of n-type impurities into corners of STI regions that are adjacent to PMOS devices.

Abstract: A new angle implant is provided that reduces or eliminates the effects of narrow channel impurity diffusion to surrounding regions of insulation. A layer of pad oxide is created over the surface of a silicon substrate, a layer of silicon nitride is deposited and patterned such that the layer of pad oxide is exposed where Shallow Trench Isolation regions are to be created. A layer of photoresist is deposited, patterned and etched to expose the surface of the p-well that has been created in the surface of the substrate, p-type impurity is then implanted into the corners of the STI region that are adjacent to NMOS device that is to be created over the p-well. The process is then repeated in reverse image order to perform a n-type implant into the corners of the STI region that are adjacent to the PMOS device that is to be created over a n-well region that has been created in the surface of the substrate.