Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a first electrode, and a second electrode. The silicon carbide substrate has a first main surface, a second main surface, a first impurity region, a second impurity region, and a third impurity region. The first electrode is in contact with each of the second impurity region and the third impurity region on the first main surface. The second electrode is in contact with the first impurity region on the second main surface. The second impurity region includes a first region and a second region disposed between the first region and the second main surface and in contact with the first region. An impurity concentration of the first region is more than or equal to 6×1016 cm?3.

Abstract: An epitaxial wafer includes a silicon carbide film having a first main surface. A groove portion is formed in the first main surface. The groove portion extends in one direction along the first main surface. Moreover, a width of the groove portion in the one direction is twice or more as large as a width of the groove portion in a direction perpendicular to the one direction. Moreover, a maximum depth of the groove portion from the first main surface is not more than 10 nm.

Abstract: An epitaxial wafer includes a silicon carbide film having a first main surface. A groove portion is formed in the first main surface. The groove portion extends in one direction along the first main surface. Moreover, a width of the groove portion in the one direction is twice or more as large as a width of the groove portion in a direction perpendicular to the one direction. Moreover, a maximum depth of the groove portion from the first main surface is not more than 10 nm.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate oxide film, and a gate electrode. A trench is provided in the main surface to have a side surface and a bottom portion. A contact point between a first side surface portion and a second side surface portion is located in a third impurity region. An angle formed by the first side surface portion and a straight line extending through the contact point and parallel to the main surface is smaller than an angle formed by the second side surface portion and a boundary surface between a first impurity region and a second impurity region. A thickness of a portion of the gate oxide film on the contact point between the main surface and the first side surface portion is larger than a thickness of a portion of the gate oxide film on the second impurity region.

Abstract: An epitaxial wafer includes a silicon carbide film having a first main surface. A groove portion is formed in the first main surface. The groove portion extends in one direction along the first main surface. Moreover, a width of the groove portion in the one direction is twice or more as large as a width of the groove portion in a direction perpendicular to the one direction. Moreover, a maximum depth of the groove portion from the first main surface is not more than 10 nm.

Abstract: An epitaxial wafer includes a silicon carbide film having a first main surface. A groove portion is formed in the first main surface. The groove portion extends in one direction along the first main surface. Moreover, a width of the groove portion in the one direction is twice or more as large as a width of the groove portion in a direction perpendicular to the one direction. Moreover, a maximum depth of the groove portion from the first main surface is not more than 10 nm.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate oxide film, and a gate electrode. A trench is provided in the main surface to have a side surface and a bottom portion. A contact point between a first side surface portion and a second side surface portion is located in a third impurity region. An angle formed by the first side surface portion and a straight line extending through the contact point and parallel to the main surface is smaller than an angle formed by the second side surface portion and a boundary surface between a first impurity region and a second impurity region. A thickness of a portion of the gate oxide film on the contact point between the main surface and the first side surface portion is larger than a thickness of a portion of the gate oxide film on the second impurity region.

Abstract: An epitaxial wafer includes a silicon carbide film having a first main surface. A groove portion is formed in the first main surface. The groove portion extends in one direction along the first main surface. Moreover, a width of the groove portion in the one direction is twice or more as large as a width of the groove portion in a direction perpendicular to the one direction. Moreover, a maximum depth of the groove portion from the first main surface is not more than 10 nm.

Abstract: A silicon carbide layer includes a first region having a first conductivity type, a second region provided on the first region and having a second conductivity type, and a third region provided on the second region and having the first conductivity type. A trench having an inner surface is formed in the silicon carbide layer. The trench penetrates the second and third regions. The inner surface of the trench has a first side wall and a second side wall located deeper than the first side wall and having a portion made of the second region. Inclination of the first side wall is smaller than inclination of the second side wall.

Abstract: Provided are a technology that simply forms a particular crystal surface such as a {03-38} surface having high carrier mobility in trench sidewalls and a SiC semiconductor element where most of the trench sidewalls appropriate for a channel member are formed from {03-38} surfaces. A trench structure formed in a (0001) surface or an off-oriented surface of a (0001) surface with an offset angle 8° or lower of SiC is provided. The channel member is in the trench structure. At least 90% of the area of the channel member is a {03-38} surface or a surface that a {03-38} surface offset by an angle from ?8° to 8° in the <1-100> direction. Specifically, the trench sidewalls are finished to {03-38} surfaces by applying a thermal etching to a trench with (0001) surfaces of SiC. Thermal etching is conducted in a chlorine atmosphere above 800° C. with nitrogen gas as the carrier.

Abstract: On a substrate, a silicon carbide layer provided with a main surface is formed. A mask is formed to cover a portion of the main surface of the silicon carbide layer. The main surface of the silicon carbide layer on which the mask is formed is thermally etched using chlorine-based gas so as to provide the silicon carbide layer with a side surface inclined relative to the main surface. The step of thermally etching is performed in an atmosphere in which the chlorine-based gas has a partial pressure of 50% or smaller.

Abstract: Provided are a technology that simply forms a particular crystal surface such as a {03-38} surface having high carrier mobility in trench sidewalls and a SiC semiconductor element where most of the trench sidewalls appropriate for a channel member are formed from {03-38} surfaces. A trench structure formed in a (0001) surface or an off-oriented surface of a (0001) surface with an offset angle 8° or lower of SiC is provided. The channel member is in the trench structure. At least 90% of the area of the channel member is a {03-38} surface or a surface that a {03-38} surface offset by an angle from ?8° to 8° in the <1-100> direction. Specifically, the trench sidewalls are finished to {03-38} surfaces by applying a thermal etching to a trench with (0001) surfaces of SiC. Thermal etching is conducted in a chlorine atmosphere above 800° C. with nitrogen gas as the carrier.

Abstract: A method for manufacturing a MOSFET includes the steps of: introducing an impurity into a silicon carbide layer; forming a carbon layer in a surface layer portion of the silicon carbide layer having the impurity introduced therein, by selectively removing silicon from the surface layer portion; and activating the impurity by heating the silicon carbide layer having the carbon layer formed therein.

Abstract: Provided is a silicon carbide semiconductor device capable of lowering the contact resistance of an ohmic electrode and achieving high reverse breakdown voltage characteristics. A semiconductor device includes a substrate and a p+ region as an impurity layer. The substrate of the first conductive type (n type) is made of silicon carbide and has a dislocation density of 5×103 cm?2 or less. The p+ region is formed on the substrate, in which the concentration of the conductive impurities having the second conductive type different from the first conductive type is 1×1020 cm3 or more and 5×1021 cm3 or less.