Patents by Inventor Tomoaki Hirokawa

Tomoaki Hirokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090288852
    Abstract: An electronic device of the present invention has a substrate; an electro-conductive pattern (electrodes) provided over the substrate; a semiconductor chip mounted over the substrate, and electrically connected with the electrodes; a resin cap provided over the substrate and composed of two or more resin layers to hollow-sealing the semiconductor chip; and an adhesive layer (metal-resin adhesion maintenance layer) bonding the resin cap with the electrode.
    Type: Application
    Filed: April 27, 2009
    Publication date: November 26, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Tomoaki Hirokawa, Makoto Matsunoshita, Yuji Kakuta, Naoki Sakura
  • Patent number: 6703678
    Abstract: A Schottky barrier field effect transistor has a gate electrode formed with a field plate in order to achieve a high withstanding voltage, where the thickness of the dielectric layer between the channel layer and the field plate, the distance between the Schottky contact and the drain and the length of the field plate falls within the range of 300 nanometers to 600 nanometers thick, the range from 800 nanometers to 3000 nanometers long and the range of the distance between the Schottky contact and the drain is plus or minus 400 nanometers, respectively, so that the distortion and the return-loss are improved without sacrifice of the withstanding voltage.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: March 9, 2004
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Tomoaki Hirokawa, Zenzou Shingu, Shigeru Saitou
  • Publication number: 20020043697
    Abstract: A Schottky barrier field effect transistor has a gate electrode formed with a field plate in order to achieve a high withstanding voltage, wherein the thickness of the dielectric layer between the channel layer and the field plate, the distance between the Schottky contact and the drain and the length of the field plate are to be fallen within the range between 300 nanometers thick to 600 nanometers thick, the range from 800 nanometers long to 3000 nanometers long and the range between the distance between the Schottky contact and the drain plus minus 400 nanometers, respectively, so that the distortion and the return-loss are improved without sacrifice of the withstanding voltage.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 18, 2002
    Applicant: NEC CORPORATION
    Inventors: Tomoaki Hirokawa, Zenzou Shingu, Shigeru Saitou
  • Patent number: 6340792
    Abstract: In a semiconductor device mold package composed of a mold cap and a mold case both of which are formed of a resin compound and which are joined to each other to form a hollow inner space defined and encapsulated by the mold cap and the mold case, the mold cap has a recess defined by an inner wall surface and surrounded by a flat mouth portion, for the purpose of forming the above mentioned hollow inner space. The mold cap is constructed to fulfill a relation of a-b≧t and a-b≦b where “a” is a height from the mouth portion to a top of an outer wall surface, “b” is a height from the mouth portion to a top of the inner wall surface, and “t” is a thickness of the mold cap at the mouth portion.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: January 22, 2002
    Assignee: NEC Corporation
    Inventor: Tomoaki Hirokawa
  • Patent number: 6011303
    Abstract: An electronic component includes a substrate portion, a bank portion, a plurality of lead members, an anchor hole, and at least a pair of notches. A chip is supported on the substrate portion. The bank portion is formed on a periphery of the substrate portion to surround the chip. The plurality of lead members are made of conductive strip pieces, and each lead member has an inner lead electrically connected to the chip and an outer lead extending to an outside. The substrate portion and the bank portion are integrally molded with a resin to include the lead members, so that the inner and outer leads are fixed to a connecting portion between the substrate portion and the bank portion. The anchor hole is formed in a portion where each of the lead members is in contact with the bank portion, and is filled with a resin. The pair of notches are formed in two ends of each of the lead members to sandwich the anchor hole.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: January 4, 2000
    Assignee: NEC Corporation
    Inventors: Junichi Tanaka, Seiji Ichikawa, Tomoaki Hirokawa, Tomoaki Kimura, Taku Sato, Kenji Watanabe, Kenji Utida, Masatoshi Ohara, Takeo Ogihara, Satoshi Murata, Tsutomu Kubota
  • Patent number: 5970322
    Abstract: An ultrahigh-frequency electronic component has an ultrahigh-frequency chip encased in a molded-resin package. The ultrahigh-frequency electronic component includes a first sealing layer encasing the ultrahigh-frequency chip therein and a second sealing layer encasing the first sealing layer therein. The first sealing layer contains a number of voids or minute air bubbles therein which are effective in reducing the permittivity of the first sealing layer. A method of manufacturing the ultrahigh-frequency electronic component is also disclosed.
    Type: Grant
    Filed: January 8, 1998
    Date of Patent: October 19, 1999
    Assignee: NEC Corporation
    Inventors: Seiji Ichikawa, Tomoaki Hirokawa, Tomoaki Kimura, Taku Sato, Junichi Tanaka, Kenji Uchida, Masatoshi Ohara, Takeo Ogihara, Satoshi Murata, Tsutomu Kubota
  • Patent number: 5956574
    Abstract: In a lead frame flash removing method and apparatus, a lead frame is molded integrally with a case. After molding, abrasive agent-mixed water is sprayed to a surface of the lead frame where a flash is formed. The lead frame is dipped in an electrolytic solution and applying a DC voltage is applied across the lead frame and an electrode in the electrolytic solution, thereby electrolytically processing the lead frame. After the electrolytic process, an external force is applied to the surface of the lead frame, thereby removing the flash.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: September 21, 1999
    Assignee: NEC Corporation
    Inventors: Seiji Ichikawa, Junichi Tanaka, Tomoaki Hirokawa, Taku Sato, Tomoaki Kimura, Satoshi Murata, Tsutomu Kubota, Takeo Ogihara, Kenji Uchida, Kenji Watanabe, Tsutomu Noguti
  • Patent number: 5904501
    Abstract: A hollow package manufacturing method includes the adhesive spreading step, the adhesive applying step, and the cap adhering step. In the adhesive spreading step, an adhesive is spread on a circular table to a uniform thickness. In the adhesive applying step, an open end face of a cylindrical cap having a bottom is urged against the circular table to apply the adhesive to the cap. In the cap adhering step, the cap applied with the adhesive is adhered to a case. A hollow package manufacturing apparatus is also disclosed.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: May 18, 1999
    Assignee: NEC Corporation
    Inventors: Masatoshi Ohara, Takeo Ogihara, Satoshi Murata, Kenji Uchida, Tsutomu Kubota, Seiji Ichikawa, Tomoaki Hirokawa, Tomoaki Kimura, Taku Sato, Junichi Tanaka
  • Patent number: 5905301
    Abstract: A package of the present invention comprises a base molded integrally with a lead frame by resin, a chip mounted on the lead frame, and a cap made of resin, which covers the chip and is fixed to the base. The base includes a substrate portion sealing the lead frame therein, a frame-shaped bank portion formed at a periphery of an upper surface of said substrate portion, the bank portion having said lead frame interposed between it snd the substrate portion, and an anchor portion formed at a portion of the lead frame interposed between the substrate portion and the bank portion. The chip is mounted on a region of the lead frame surrounded by the bank portion. The cap is fixed to the bank portion.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: May 18, 1999
    Assignee: NEC Corporation
    Inventors: Seiji Ichikawa, Tomoaki Hirokawa, Tomoaki Kimura, Junichi Tanaka, Taku Sato, Satoshi Murata, Tsutomu Kubota, Takeo Ogihara, Kenji Uchida
  • Patent number: 5889232
    Abstract: An ultrahigh-frequency electronic component has an ultrahigh-frequency chip encased in a molded-resin package. The ultrahigh-frequency electronic component includes a first sealing layer encasing the ultrahigh-frequency chip therein and a second sealing layer encasing the first sealing layer therein. The first sealing layer contains a number of voids or minute air bubbles therein which are effective in reducing the permittivity of the first sealing layer. A method of manufacturing the ultrahigh-frequency electronic component is also disclosed.
    Type: Grant
    Filed: May 13, 1997
    Date of Patent: March 30, 1999
    Assignee: NEC Corporation
    Inventors: Seiji Ichikawa, Tomoaki Hirokawa, Tomoaki Kimura, Taku Sato, Junichi Tanaka, Kenji Uchida, Masatoshi Ohara, Takeo Ogihara, Satoshi Murata, Tsutomu Kubota