Patents by Inventor Tomoaki Inaoka

Tomoaki Inaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor wafer and method for manufacturing semiconductor device
    Patent number: 9508559
    Abstract: A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: November 29, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shoko Saito, Tomoyuki Okada, Kanji Takeuchi, Mitsufumi Naoe, Masahiko Minemura, Yukihiro Sato, Yoshito Konno, Yasuhiko Inada, Tomoaki Inaoka, Naoya Sashida
  • SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20140110712
    Abstract: A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner.
    Type: Application
    Filed: September 18, 2013
    Publication date: April 24, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shoko Saito, Tomoyuki Okada, Kanji Takeuchi, MITSUFUMI NAOE, Masahiko Minemura, Yukihiro Sato, Yoshito Konno, Yasuhiko Inada, Tomoaki Inaoka, Naoya SASHIDA
  • Random number generation device and method, generator evaluation method and method for using random numbers
    Publication number: 20070067375
    Abstract: A random number generation device, comprising: a random number generation unit for generating random numbers; a random number generation control unit for providing parameters for enabling the random generation unit to generate random numbers; and a randomness determination unit for determining the randomness of each generated random number, wherein if the randomness of a generated random number does not meet a predetermined condition, the random number generation control unit updates the parameters for generating a random number to enable the random number generation unit to generate a new random number.
    Type: Application
    Filed: November 20, 2006
    Publication date: March 22, 2007
    Inventors: Tomoaki Inaoka, Shunsuke Fueki