Patents by Inventor Tomoaki Isozaki
Tomoaki Isozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9762244Abstract: A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal.Type: GrantFiled: June 30, 2015Date of Patent: September 12, 2017Assignee: Renesas Electronics CorporationInventor: Tomoaki Isozaki
-
Publication number: 20150303924Abstract: A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal.Type: ApplicationFiled: June 30, 2015Publication date: October 22, 2015Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Tomoaki ISOZAKI
-
Patent number: 9099330Abstract: A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal.Type: GrantFiled: January 7, 2013Date of Patent: August 4, 2015Assignee: Renesas Electronics CorporationInventor: Tomoaki Isozaki
-
Patent number: 8350593Abstract: A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal.Type: GrantFiled: January 27, 2011Date of Patent: January 8, 2013Assignee: Renesas Electronics CorporationInventor: Tomoaki Isozaki
-
Publication number: 20110133803Abstract: A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal.Type: ApplicationFiled: January 27, 2011Publication date: June 9, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Tomoaki ISOZAKI
-
Patent number: 7902873Abstract: A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal.Type: GrantFiled: November 20, 2006Date of Patent: March 8, 2011Assignee: Renesas Electronics CorporationInventor: Tomoaki Isozaki
-
Patent number: 7400134Abstract: The integrated circuit device includes a memory chip and a logic chip. The memory chip has memory I/O pads and test pads. The test pads are placed in line at the position outer than memory I/O pads and larger than the memory I/O pads. The logic chip has logic COC I/O pads. The logic COC I/O pads are connected to the memory I/O pads.Type: GrantFiled: January 19, 2005Date of Patent: July 15, 2008Assignee: NEC Electronics CorporationInventors: Yoshiaki Morishita, Nobuteru Oh, Tomoaki Isozaki
-
Publication number: 20070114571Abstract: A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal.Type: ApplicationFiled: November 20, 2006Publication date: May 24, 2007Inventor: Tomoaki ISOZAKI
-
Publication number: 20060050454Abstract: A chip-on-chip semiconductor device is composed of: a first chip operating on a first power supply voltage; and a second chip operating on a second power supply voltage lower than the first power supply voltage, the first and second chips being flip-chip connected through inter-chip connection bumps. The second chip is designed to provide level-conversion for a transmission signal received from the first chip.Type: ApplicationFiled: September 6, 2005Publication date: March 9, 2006Inventors: Kazuhiro Koudate, Tomoaki Isozaki
-
Publication number: 20050156616Abstract: The integrated circuit device includes a memory chip and a logic chip. The memory chip has memory I/O pads and test pads. The test pads are placed in line at the position outer than memory I/O pads and larger than the memory I/O pads. The logic chip has logic COC I/O pads. The logic COC I/O pads are connected to the memory I/O pads.Type: ApplicationFiled: January 19, 2005Publication date: July 21, 2005Inventors: Yoshiaki Morishita, Nobuteru Oh, Tomoaki Isozaki
-
Patent number: 5292687Abstract: A pad is provided outside a pad block. The most appropriate position is determined for the pad which is connected to the pad block. The pad block is arranged to be most appropriate in position relative to the pad, and a coordinate of the pad block is determined to be used for interconnection of internal regions of the pad block.Type: GrantFiled: February 7, 1992Date of Patent: March 8, 1994Assignee: NEC CorporationInventor: Tomoaki Isozaki
-
Patent number: 4805508Abstract: A sound synthesizing circuit has means for synthesizing sound digital data in a pitch period of a sound to be synthesized and means for producing a sound analog signal according to the synthesized sound digital data. The synthesized sound digital data are sequentially transferred to the producing means according to a sequential sampling pulse. The sequential sampling pulse has a predetermined interval and a corrected interval different from the predetermined interval in one pitch period of a sound to be synthesized. Thus, a sound of good quality with an arbitrary interval can be synthesized in a wide scale by a simple hardware integrated circuit in a small semiconductor chip.Type: GrantFiled: July 24, 1987Date of Patent: February 21, 1989Assignee: NEC CorporationInventor: Tomoaki Isozaki